Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher

Differential Fault Analysis (DFA) and Power Analysis (PA) attacks, have become the main methods for exploiting the vulnerabilities of physical implementations of block ciphers, currently used in a multitude of applications, such as the Advanced Encryption Standard (AES). In order to minimize these t...

ver descrição completa

Detalhes bibliográficos
Autores: Potestad Ordóñez, Francisco Eugenio, Tena Sánchez, Erica, Acosta Jiménez, Antonio José, Jiménez Fernández, Carlos Jesús, Chaves, Ricardo
Tipo de documento: artigo
Estado:Versão publicada
Data de publicação:2022
País:España
Recursos:Universidad de Sevilla (US)
Repositório:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/141397
Acesso em linha:https://hdl.handle.net/11441/141397
https://doi.org/10.1109/ACCESS.2022.3183764
Access Level:Acceso aberto
Palavra-chave:Countermeasure
FPGA implementation
Hamming code
Parity
AES
DFA
Fault attack
Power analysis
id ES_abb226cbdee44cbb33da6385ecf91e93
oai_identifier_str oai:idus.us.es:11441/141397
network_acronym_str ES
network_name_str España
repository_id_str
spelling Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipherPotestad Ordóñez, Francisco EugenioTena Sánchez, EricaAcosta Jiménez, Antonio JoséJiménez Fernández, Carlos JesúsChaves, RicardoCountermeasureFPGA implementationHamming codeParityAESDFAFault attackPower analysisDifferential Fault Analysis (DFA) and Power Analysis (PA) attacks, have become the main methods for exploiting the vulnerabilities of physical implementations of block ciphers, currently used in a multitude of applications, such as the Advanced Encryption Standard (AES). In order to minimize these types of vulnerabilities, several mechanisms have been proposed to detect fault attacks. However, these mechanisms can have a signi cant cost, not fully covering the implementations against fault attacks or not taking into account the leakage of the information exploitable by the power analysis attacks. In this paper, four different approaches are proposed with the aim of protecting the AES block cipher against DFA. The proposed solutions are based on Hamming code and parity bits as signature generators for the internal state of the AES cipher. These allow to detect DFA exploitable faults, from bit to byte level. The proposed solutions have been applied to a T-box based AES block cipher implemented on Field Programmable Gate Array (FPGA). Experimental results suggest a fault coverage of 98.5% and 99.99% with an area penalty of 9% and 36% respectively, for the parity bit signature generators and a fault coverage of 100% with an area penalty of 18% and 42% respectively when Hamming code signature generator is used. In addition, none of the proposed countermeasures impose a frequency degradation, in respect to the unprotected cipher. The proposed work goes further in the evaluation of the proposed DFA countermeasures by evaluating the impact of these structures in terms of power side-channel. The obtained results suggest that no extra information leakage is produced that can be exploited by PA. Overall, the proposed DFA countermeasures provide a high fault coverage protection with a low cost in terms of area and power consumption and no PA security degradation.IEEETecnología ElectrónicaElectrónica y ElectromagnetismoTIC180: Diseño de Circuitos Integrados Digitales y MixtosUniversidad de Sevilla/Junta de Andalucía/Fondos FEDER, UE SCAROT 1380823European Regional Development Fund (EU) FCT: UIDB/50021/20202022info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/141397https://doi.org/10.1109/ACCESS.2022.3183764reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésIEEE Access, 10, 65548-65561.SCAROT 1380823FCT: UIDB/50021/2020https://ieeexplore.ieee.org/document/9797724info:eu-repo/semantics/openAccessoai:idus.us.es:11441/1413972026-06-17T12:51:07Z
dc.title.none.fl_str_mv Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher
title Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher
spellingShingle Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher
Potestad Ordóñez, Francisco Eugenio
Countermeasure
FPGA implementation
Hamming code
Parity
AES
DFA
Fault attack
Power analysis
title_short Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher
title_full Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher
title_fullStr Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher
title_full_unstemmed Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher
title_sort Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher
dc.creator.none.fl_str_mv Potestad Ordóñez, Francisco Eugenio
Tena Sánchez, Erica
Acosta Jiménez, Antonio José
Jiménez Fernández, Carlos Jesús
Chaves, Ricardo
author Potestad Ordóñez, Francisco Eugenio
author_facet Potestad Ordóñez, Francisco Eugenio
Tena Sánchez, Erica
Acosta Jiménez, Antonio José
Jiménez Fernández, Carlos Jesús
Chaves, Ricardo
author_role author
author2 Tena Sánchez, Erica
Acosta Jiménez, Antonio José
Jiménez Fernández, Carlos Jesús
Chaves, Ricardo
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Tecnología Electrónica
Electrónica y Electromagnetismo
TIC180: Diseño de Circuitos Integrados Digitales y Mixtos
Universidad de Sevilla/Junta de Andalucía/Fondos FEDER, UE SCAROT 1380823
European Regional Development Fund (EU) FCT: UIDB/50021/2020
dc.subject.none.fl_str_mv Countermeasure
FPGA implementation
Hamming code
Parity
AES
DFA
Fault attack
Power analysis
topic Countermeasure
FPGA implementation
Hamming code
Parity
AES
DFA
Fault attack
Power analysis
description Differential Fault Analysis (DFA) and Power Analysis (PA) attacks, have become the main methods for exploiting the vulnerabilities of physical implementations of block ciphers, currently used in a multitude of applications, such as the Advanced Encryption Standard (AES). In order to minimize these types of vulnerabilities, several mechanisms have been proposed to detect fault attacks. However, these mechanisms can have a signi cant cost, not fully covering the implementations against fault attacks or not taking into account the leakage of the information exploitable by the power analysis attacks. In this paper, four different approaches are proposed with the aim of protecting the AES block cipher against DFA. The proposed solutions are based on Hamming code and parity bits as signature generators for the internal state of the AES cipher. These allow to detect DFA exploitable faults, from bit to byte level. The proposed solutions have been applied to a T-box based AES block cipher implemented on Field Programmable Gate Array (FPGA). Experimental results suggest a fault coverage of 98.5% and 99.99% with an area penalty of 9% and 36% respectively, for the parity bit signature generators and a fault coverage of 100% with an area penalty of 18% and 42% respectively when Hamming code signature generator is used. In addition, none of the proposed countermeasures impose a frequency degradation, in respect to the unprotected cipher. The proposed work goes further in the evaluation of the proposed DFA countermeasures by evaluating the impact of these structures in terms of power side-channel. The obtained results suggest that no extra information leakage is produced that can be exploited by PA. Overall, the proposed DFA countermeasures provide a high fault coverage protection with a low cost in terms of area and power consumption and no PA security degradation.
publishDate 2022
dc.date.none.fl_str_mv 2022
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/141397
https://doi.org/10.1109/ACCESS.2022.3183764
url https://hdl.handle.net/11441/141397
https://doi.org/10.1109/ACCESS.2022.3183764
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv IEEE Access, 10, 65548-65561.
SCAROT 1380823
FCT: UIDB/50021/2020
https://ieeexplore.ieee.org/document/9797724
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv IEEE
publisher.none.fl_str_mv IEEE
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869416291352182784
score 15,301603

Registros relacionados