GPU versus FPGA implementation of a digital predistortion linearizer for wideband radiofrequency power amplifiers
This paper presents and compares the implementation of a digital predistortion (DPD) linearizer for radiofrequency power amplifiers (PAs) considering two different hardware acceleration platforms. Both graphics processing unit (GPU)-based and field programmable gate arrays (FPGA)-based implementatio...
| Autores: | , , |
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| Formato: | artículo |
| Fecha de publicación: | 2024 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/406446 |
| Acesso em linha: | https://hdl.handle.net/2117/406446 https://dx.doi.org/10.1016/j.aeue.2023.155040 |
| Access Level: | acceso abierto |
| Palavra-chave: | Power amplifiers Power amplifier Digital predistortion Linearization Field programmable gate arrays Graphics processing unit Amplificadors de potència Àrees temàtiques de la UPC::Enginyeria de la telecomunicació |
| Resumo: | This paper presents and compares the implementation of a digital predistortion (DPD) linearizer for radiofrequency power amplifiers (PAs) considering two different hardware acceleration platforms. Both graphics processing unit (GPU)-based and field programmable gate arrays (FPGA)-based implementations of the DPD are capable to meet the high throughput requirements for linearizing the PA with current 5G new radio (NR) wideband signals. A comparison in terms of hardware resources usage, precision, throughput and linearization performance is provided for both GPU and FPGA implementations of a DPD based on the generalized memory polynomial (GMP) behavioral model. |
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