Systolic architectures for fuzzy processing and their simulation
This paper details the study of systolic architectures for fuzzy rules processing made at the Hardware and Advanced Control Laboratory - INTA. The theoretical basis of these architectures is described and analysed. Likewise, the resultant schematics are simulated using a hardware description languag...
| Autores: | , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 1994 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2099/2458 |
| Acceso en línea: | https://hdl.handle.net/2099/2458 |
| Access Level: | acceso abierto |
| Palabra clave: | Fuzzy Control Systolic Simulation VHDL Sistemes de control intel·ligents Lògica difusa VHDL (Llenguatge de descripció de hardware) Classificació AMS::68 Computer science::68Q Theory of computing |
| Sumario: | This paper details the study of systolic architectures for fuzzy rules processing made at the Hardware and Advanced Control Laboratory - INTA. The theoretical basis of these architectures is described and analysed. Likewise, the resultant schematics are simulated using a hardware description language (VHDL) with standard cells from ES2. This gives us a very accurate assessment of their real performance. In this way we can detect the inherent shortcomings in this class of systems and we outline several ways of overcoming then. |
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