Implementation of Background Calibration for Redundant FLASH ADC

Flash converters are suitable analog-to-digital converter architectures for high-speed applications. However, the benefits in terms of the frequency of smaller technology nodes are hampered by variability, which necessitates the use of large transistors. Comparator redundancy was introduced to overc...

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Detalles Bibliográficos
Autores: Darwish, Hala, Reig, Candid, Leger, Gildas
Tipo de recurso: artículo
Estado:Versión publicada
Fecha de publicación:2023
País:España
Institución:Consejo Superior de Investigaciones Científicas (CSIC)
Repositorio:DIGITAL.CSIC. Repositorio Institucional del CSIC
OAI Identifier:oai:digital.csic.es:10261/340156
Acceso en línea:http://hdl.handle.net/10261/340156
Access Level:acceso abierto
Palabra clave:Calibration stimulus generator
Control unit algorithm
Flash converter
Online calibration
Redundancy system
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spelling Implementation of Background Calibration for Redundant FLASH ADCDarwish, HalaReig, CandidLeger, GildasCalibration stimulus generatorControl unit algorithmFlash converterOnline calibrationRedundancy systemFlash converters are suitable analog-to-digital converter architectures for high-speed applications. However, the benefits in terms of the frequency of smaller technology nodes are hampered by variability, which necessitates the use of large transistors. Comparator redundancy was introduced to overcome this trade-off; the best comparators were selected upfront (either at start-up or in the factory), and the unused comparators could be switched off. This work studies the possibility of performing comparator selection in the background concurrently with normal conversion to increase the converter lifetime. Thus, the system can automatically recover its performance from drifts or failures due to aging, temperature, etc. This paper proposes an embedded solution that includes a calibration stimulus generator (which only requires some external passive elements) and develops system design requirements. In addition, mathematical equations and error sensitivities of the system elements were derived. A 6b flash converter is implemented in UMC180nm technology, and transistor-level simulations of the system are provided to demonstrate the feasibility of the proposed system.This work was funded in part by the Spanish Government under Project RTI2018-098513-B-I00 and Project PID2019-105556GB-C32 (co-funded by FEDER program).Peer reviewedMultidisciplinary Digital Publishing InstituteMinisterio de Ciencia, Innovación y Universidades (España)Agencia Estatal de Investigación (España)Consejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]2023202320232023info:eu-repo/semantics/articlehttp://purl.org/coar/resource_type/c_6501Publisher's versioninfo:eu-repo/semantics/publishedVersionapplication/pdfhttp://hdl.handle.net/10261/340156reponame:DIGITAL.CSIC. Repositorio Institucional del CSICinstname:Consejo Superior de Investigaciones Científicas (CSIC)Inglés#PLACEHOLDER_PARENT_METADATA_VALUE##PLACEHOLDER_PARENT_METADATA_VALUE#info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/RTI2018-098513-B-I00info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-105556GB-C32https://doi.org/10.3390/electronics12224559Síinfo:eu-repo/semantics/openAccessoai:digital.csic.es:10261/3401562026-05-22T06:33:51Z
dc.title.none.fl_str_mv Implementation of Background Calibration for Redundant FLASH ADC
title Implementation of Background Calibration for Redundant FLASH ADC
spellingShingle Implementation of Background Calibration for Redundant FLASH ADC
Darwish, Hala
Calibration stimulus generator
Control unit algorithm
Flash converter
Online calibration
Redundancy system
title_short Implementation of Background Calibration for Redundant FLASH ADC
title_full Implementation of Background Calibration for Redundant FLASH ADC
title_fullStr Implementation of Background Calibration for Redundant FLASH ADC
title_full_unstemmed Implementation of Background Calibration for Redundant FLASH ADC
title_sort Implementation of Background Calibration for Redundant FLASH ADC
dc.creator.none.fl_str_mv Darwish, Hala
Reig, Candid
Leger, Gildas
author Darwish, Hala
author_facet Darwish, Hala
Reig, Candid
Leger, Gildas
author_role author
author2 Reig, Candid
Leger, Gildas
author2_role author
author
dc.contributor.none.fl_str_mv Ministerio de Ciencia, Innovación y Universidades (España)
Agencia Estatal de Investigación (España)
Consejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]
dc.subject.none.fl_str_mv Calibration stimulus generator
Control unit algorithm
Flash converter
Online calibration
Redundancy system
topic Calibration stimulus generator
Control unit algorithm
Flash converter
Online calibration
Redundancy system
description Flash converters are suitable analog-to-digital converter architectures for high-speed applications. However, the benefits in terms of the frequency of smaller technology nodes are hampered by variability, which necessitates the use of large transistors. Comparator redundancy was introduced to overcome this trade-off; the best comparators were selected upfront (either at start-up or in the factory), and the unused comparators could be switched off. This work studies the possibility of performing comparator selection in the background concurrently with normal conversion to increase the converter lifetime. Thus, the system can automatically recover its performance from drifts or failures due to aging, temperature, etc. This paper proposes an embedded solution that includes a calibration stimulus generator (which only requires some external passive elements) and develops system design requirements. In addition, mathematical equations and error sensitivities of the system elements were derived. A 6b flash converter is implemented in UMC180nm technology, and transistor-level simulations of the system are provided to demonstrate the feasibility of the proposed system.
publishDate 2023
dc.date.none.fl_str_mv 2023
2023
2023
2023
dc.type.none.fl_str_mv info:eu-repo/semantics/article
http://purl.org/coar/resource_type/c_6501
Publisher's version
info:eu-repo/semantics/publishedVersion
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/10261/340156
url http://hdl.handle.net/10261/340156
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv #PLACEHOLDER_PARENT_METADATA_VALUE#
#PLACEHOLDER_PARENT_METADATA_VALUE#
info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/RTI2018-098513-B-I00
info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-105556GB-C32
https://doi.org/10.3390/electronics12224559
Sí
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Multidisciplinary Digital Publishing Institute
publisher.none.fl_str_mv Multidisciplinary Digital Publishing Institute
dc.source.none.fl_str_mv reponame:DIGITAL.CSIC. Repositorio Institucional del CSIC
instname:Consejo Superior de Investigaciones Científicas (CSIC)
instname_str Consejo Superior de Investigaciones Científicas (CSIC)
reponame_str DIGITAL.CSIC. Repositorio Institucional del CSIC
collection DIGITAL.CSIC. Repositorio Institucional del CSIC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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