Double–frequency buck converter as a candidate topology for integrated envelope elimination and restoration applications in power supply of RFPAs
This paper proposes the use of double-frequency (DF) buck converter architecture consisting of a merged structure of high and low frequency buck cells as a candidate topology for envelope elimination and restoration (EER) applications and integrated power Supply of RF power amplifiers (RFPA) to obta...
| Autores: | , , , |
|---|---|
| Formato: | artículo |
| Fecha de publicación: | 2016 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/116573 |
| Acesso em linha: | https://hdl.handle.net/2117/116573 https://dx.doi.org/10.1002/cta.2155 |
| Access Level: | acceso abierto |
| Palavra-chave: | Electric current converters Buck converter double-frequency efficiency envelope elimination and restoration (EER) output ripple. Convertidors de corrent elèctric Àrees temàtiques de la UPC::Enginyeria electrònica Àrees temàtiques de la UPC::Enginyeria elèctrica |
| Resumo: | This paper proposes the use of double-frequency (DF) buck converter architecture consisting of a merged structure of high and low frequency buck cells as a candidate topology for envelope elimination and restoration (EER) applications and integrated power Supply of RF power amplifiers (RFPA) to obtain favorable tradeoffs in terms of efficiency, switching ripple, bandwidth, and tracking capability. It is shown that having two degrees of freedom in designing the DF buck helps to achieve high efficiency, low output ripples, and tracking capability with low ripples, simultaneously. A comparison analysis is done with regards to the mentioned performance indexes with the standard and three-level buck converters; in addition, the results are validated in HSPICE in BSIM3V3 0.35-µm CMOS process. |
|---|