Cache-Hierarchy contention-aware scheduling in CMPs

To improve chip multiprocessor (CMP) performance, recent research has focused on scheduling strategies to mitigate main memory bandwidth contention. Nowadays, commercial CMPs implement multilevel cache hierarchies that are shared by several multithreaded cores. In this microprocessor design, content...

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Detalhes bibliográficos
Autores: Feliu-Pérez, Josué|||0000-0003-3017-4266, Petit Martí, Salvador Vicente|||0000-0003-2426-4134, Sahuquillo Borrás, Julio|||0000-0001-8630-4846, Duato Marín, José Francisco
Formato: artículo
Fecha de publicación:2014
País:España
Recursos:Universitat Politècnica de València (UPV)
Repositorio:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
Idioma:inglés
OAI Identifier:oai:riunet.upv.es:10251/49705
Acesso em linha:https://riunet.upv.es/handle/10251/49705
Access Level:acceso abierto
Palavra-chave:Contention-aware scheduling
Contention points
Shared caches
Cache hierarchy
Memory contention
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
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network_name_str España
repository_id_str
spelling Cache-Hierarchy contention-aware scheduling in CMPsFeliu-Pérez, Josué|||0000-0003-3017-4266Petit Martí, Salvador Vicente|||0000-0003-2426-4134Sahuquillo Borrás, Julio|||0000-0001-8630-4846Duato Marín, José FranciscoContention-aware schedulingContention pointsShared cachesCache hierarchyMemory contentionARQUITECTURA Y TECNOLOGIA DE COMPUTADORESTo improve chip multiprocessor (CMP) performance, recent research has focused on scheduling strategies to mitigate main memory bandwidth contention. Nowadays, commercial CMPs implement multilevel cache hierarchies that are shared by several multithreaded cores. In this microprocessor design, contention points may appear along the whole memory hierarchy. Moreover, this problem is expected to aggravate in future technologies, since the number of cores and hardware threads, and consequently the size of the shared caches increase with each microprocessor generation. This paper characterizes the impact on performance of the different contention points that appear along the memory subsystem. The analysis shows that some benchmarks are more sensitive to contention in higher levels of the memory hierarchy (e.g., shared L2) than to main memory contention. In this paper, we propose two generic scheduling strategies for CMPs. The first strategy takes into account the available bandwidth at each level of the cache hierarchy. The strategy selects the processes to be coscheduled and allocates them to cores to minimize contention effects. The second strategy also considers the performance degradation each process suffers due to contention-aware scheduling. Both proposals have been implemented and evaluated in a commercial single-threaded quad-core processor with a relatively small two-level cache hierarchy. The proposals reach, on average, a performance improvement by 5.38 and 6.64 percent when compared with the Linux scheduler, while this improvement is by 3.61 percent for an state-of-the-art memory contention-aware scheduler under the evaluated mixes.This work was supported by the Spanish MINECO under Grant TIN2012-38341-C04-01, and by the Universitat Politecnica de Valencia under Grant PAID-05-12 SP20120748.Institute of Electrical and Electronics Engineers (IEEE)Departamento de Informática de Sistemas y ComputadoresEscuela Técnica Superior de Ingeniería InformáticaGrupo de Arquitecturas ParalelasUniversitat Politècnica de ValènciaMinisterio de Economía y CompetitividadRepositorio Institucional de la Universitat Politècnica de València Riunet20142014-03-01journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfapplication/pdfhttps://riunet.upv.es/handle/10251/49705reponame:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valénciainstname:Universitat Politècnica de València (UPV)InglésengMinisterio de Economía y Competitividad http://dx.doi.org/10.13039/501100003329 TIN2012-38341-C04-01 MEJORA DE LA ARQUITECTURA DE SERVIDORES, SERVICIOS Y APLICACIONESUniversitat Politècnica de València https://doi.org/10.13039/501100004233 PAID-05-12-SP20120748open accesshttp://purl.org/coar/access_right/c_abf2Reserva de todos los derechoshttp://rightsstatements.org/vocab/InC/1.0/info:eu-repo/semantics/openAccessoai:riunet.upv.es:10251/497052026-06-13T07:49:27Z
dc.title.none.fl_str_mv Cache-Hierarchy contention-aware scheduling in CMPs
title Cache-Hierarchy contention-aware scheduling in CMPs
spellingShingle Cache-Hierarchy contention-aware scheduling in CMPs
Feliu-Pérez, Josué|||0000-0003-3017-4266
Contention-aware scheduling
Contention points
Shared caches
Cache hierarchy
Memory contention
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
title_short Cache-Hierarchy contention-aware scheduling in CMPs
title_full Cache-Hierarchy contention-aware scheduling in CMPs
title_fullStr Cache-Hierarchy contention-aware scheduling in CMPs
title_full_unstemmed Cache-Hierarchy contention-aware scheduling in CMPs
title_sort Cache-Hierarchy contention-aware scheduling in CMPs
dc.creator.none.fl_str_mv Feliu-Pérez, Josué|||0000-0003-3017-4266
Petit Martí, Salvador Vicente|||0000-0003-2426-4134
Sahuquillo Borrás, Julio|||0000-0001-8630-4846
Duato Marín, José Francisco
author Feliu-Pérez, Josué|||0000-0003-3017-4266
author_facet Feliu-Pérez, Josué|||0000-0003-3017-4266
Petit Martí, Salvador Vicente|||0000-0003-2426-4134
Sahuquillo Borrás, Julio|||0000-0001-8630-4846
Duato Marín, José Francisco
author_role author
author2 Petit Martí, Salvador Vicente|||0000-0003-2426-4134
Sahuquillo Borrás, Julio|||0000-0001-8630-4846
Duato Marín, José Francisco
author2_role author
author
author
dc.contributor.none.fl_str_mv Departamento de Informática de Sistemas y Computadores
Escuela Técnica Superior de Ingeniería Informática
Grupo de Arquitecturas Paralelas
Universitat Politècnica de València
Ministerio de Economía y Competitividad
Repositorio Institucional de la Universitat Politècnica de València Riunet
dc.subject.none.fl_str_mv Contention-aware scheduling
Contention points
Shared caches
Cache hierarchy
Memory contention
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
topic Contention-aware scheduling
Contention points
Shared caches
Cache hierarchy
Memory contention
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
description To improve chip multiprocessor (CMP) performance, recent research has focused on scheduling strategies to mitigate main memory bandwidth contention. Nowadays, commercial CMPs implement multilevel cache hierarchies that are shared by several multithreaded cores. In this microprocessor design, contention points may appear along the whole memory hierarchy. Moreover, this problem is expected to aggravate in future technologies, since the number of cores and hardware threads, and consequently the size of the shared caches increase with each microprocessor generation. This paper characterizes the impact on performance of the different contention points that appear along the memory subsystem. The analysis shows that some benchmarks are more sensitive to contention in higher levels of the memory hierarchy (e.g., shared L2) than to main memory contention. In this paper, we propose two generic scheduling strategies for CMPs. The first strategy takes into account the available bandwidth at each level of the cache hierarchy. The strategy selects the processes to be coscheduled and allocates them to cores to minimize contention effects. The second strategy also considers the performance degradation each process suffers due to contention-aware scheduling. Both proposals have been implemented and evaluated in a commercial single-threaded quad-core processor with a relatively small two-level cache hierarchy. The proposals reach, on average, a performance improvement by 5.38 and 6.64 percent when compared with the Linux scheduler, while this improvement is by 3.61 percent for an state-of-the-art memory contention-aware scheduler under the evaluated mixes.
publishDate 2014
dc.date.none.fl_str_mv 2014
2014-03-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://riunet.upv.es/handle/10251/49705
url https://riunet.upv.es/handle/10251/49705
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.relation.none.fl_str_mv Ministerio de Economía y Competitividad http://dx.doi.org/10.13039/501100003329 TIN2012-38341-C04-01 MEJORA DE LA ARQUITECTURA DE SERVIDORES, SERVICIOS Y APLICACIONES
Universitat Politècnica de València https://doi.org/10.13039/501100004233 PAID-05-12-SP20120748
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Reserva de todos los derechos
http://rightsstatements.org/vocab/InC/1.0/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Reserva de todos los derechos
http://rightsstatements.org/vocab/InC/1.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers (IEEE)
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers (IEEE)
dc.source.none.fl_str_mv reponame:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname:Universitat Politècnica de València (UPV)
instname_str Universitat Politècnica de València (UPV)
reponame_str RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
collection RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,301603

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