On the maturity of parallel applications for asymmetric multi-core processors

Asymmetric multi-cores (AMCs) are a successful architectural solution for both mobile devices and supercomputers. By maintaining two types of cores (fast and slow) AMCs are able to provide high performance under the facility power budget. This paper performs the first extensive evaluation of how por...

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Autores: Chronaki, Kallia, Moretó Planas, Miquel|||0000-0002-9848-8758, Casas, Marc|||0000-0003-4564-2093, Rico, Alejandro, Badia Sala, Rosa Maria|||0000-0003-2941-5499, Ayguadé Parra, Eduard|||0000-0002-5146-103X, Valero Cortés, Mateo|||0000-0003-2917-2482
Tipo de recurso: artículo
Fecha de publicación:2019
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/133416
Acceso en línea:https://hdl.handle.net/2117/133416
https://dx.doi.org/10.1016/j.jpdc.2019.01.007
Access Level:acceso abierto
Palabra clave:Supercomputers
High performance computing
Parallel programming (Computer science)
Scheduling
Runtime systems
Asymmetric multi-cores
HPC
Superordinadors
Càlcul intensiu (Informàtica)
Programació en paral·lel (Informàtica)
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
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spelling On the maturity of parallel applications for asymmetric multi-core processorsChronaki, KalliaMoretó Planas, Miquel|||0000-0002-9848-8758Casas, Marc|||0000-0003-4564-2093Rico, AlejandroBadia Sala, Rosa Maria|||0000-0003-2941-5499Ayguadé Parra, Eduard|||0000-0002-5146-103XValero Cortés, Mateo|||0000-0003-2917-2482SupercomputersHigh performance computingParallel programming (Computer science)SchedulingRuntime systemsAsymmetric multi-coresHPCSuperordinadorsCàlcul intensiu (Informàtica)Programació en paral·lel (Informàtica)Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadorsAsymmetric multi-cores (AMCs) are a successful architectural solution for both mobile devices and supercomputers. By maintaining two types of cores (fast and slow) AMCs are able to provide high performance under the facility power budget. This paper performs the first extensive evaluation of how portable are the current HPC applications for such supercomputing systems. Specifically we evaluate several execution models on an ARM big.LITTLE AMC using the PARSEC benchmark suite that includes representative highly parallel applications. We compare schedulers at the user, OS and runtime levels, using both static and dynamic options and multiple configurations, and assess the impact of these options on the well-known problem of balancing the load across AMCs. Our results demonstrate that scheduling is more effective when it takes place in the runtime system level as it improves the baseline by 23%, while the heterogeneous-aware OS scheduling solution improves the baseline by 10%.This work has been supported by the RoMoL ERC Advanced Grant (GA 321253), by the European HiPEAC Network of Excellence, by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P), by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), and by the European Union's Horizon 2020 research and innovation programme under grant agreement No 671697 and No. 779877. M. Moretó has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal fellowship number RYC-2016-21104.Peer ReviewedElsevier20192019-05-0120192019-05-24journal articlehttp://purl.org/coar/resource_type/c_6501AMhttp://purl.org/coar/version/c_ab4af688f83e57aainfo:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/2117/133416https://dx.doi.org/10.1016/j.jpdc.2019.01.007reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)InglésengMinisterio de Economía y Competitividad http://doi.org/10.13039/501100003329 TIN2015-65316-P COMPUTACION DE ALTAS PRESTACIONES VIIEuropean Commission http://dx.doi.org/10.13039/100011102 Seventh Framework Programme 321253 Riding on Moore's LawEuropean Commission http://doi.org/10.13039/100010661 Horizon 2020 Framework Programme 671697 Mont-Blanc 3, European scalable and power efficient HPC platform based on low-power embedded technologyEuropean Commission http://doi.org/10.13039/100010661 Horizon 2020 Framework Programme 779877 Mont-Blanc 2020, European scalable, modular and power efficient HPC processoropen accesshttp://purl.org/coar/access_right/c_abf2Attribution-NonCommercial-NoDerivs 3.0 Spainhttp://creativecommons.org/licenses/by-nc-nd/3.0/es/info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/1334162026-05-27T15:37:01Z
dc.title.none.fl_str_mv On the maturity of parallel applications for asymmetric multi-core processors
title On the maturity of parallel applications for asymmetric multi-core processors
spellingShingle On the maturity of parallel applications for asymmetric multi-core processors
Chronaki, Kallia
Supercomputers
High performance computing
Parallel programming (Computer science)
Scheduling
Runtime systems
Asymmetric multi-cores
HPC
Superordinadors
Càlcul intensiu (Informàtica)
Programació en paral·lel (Informàtica)
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
title_short On the maturity of parallel applications for asymmetric multi-core processors
title_full On the maturity of parallel applications for asymmetric multi-core processors
title_fullStr On the maturity of parallel applications for asymmetric multi-core processors
title_full_unstemmed On the maturity of parallel applications for asymmetric multi-core processors
title_sort On the maturity of parallel applications for asymmetric multi-core processors
dc.creator.none.fl_str_mv Chronaki, Kallia
Moretó Planas, Miquel|||0000-0002-9848-8758
Casas, Marc|||0000-0003-4564-2093
Rico, Alejandro
Badia Sala, Rosa Maria|||0000-0003-2941-5499
Ayguadé Parra, Eduard|||0000-0002-5146-103X
Valero Cortés, Mateo|||0000-0003-2917-2482
author Chronaki, Kallia
author_facet Chronaki, Kallia
Moretó Planas, Miquel|||0000-0002-9848-8758
Casas, Marc|||0000-0003-4564-2093
Rico, Alejandro
Badia Sala, Rosa Maria|||0000-0003-2941-5499
Ayguadé Parra, Eduard|||0000-0002-5146-103X
Valero Cortés, Mateo|||0000-0003-2917-2482
author_role author
author2 Moretó Planas, Miquel|||0000-0002-9848-8758
Casas, Marc|||0000-0003-4564-2093
Rico, Alejandro
Badia Sala, Rosa Maria|||0000-0003-2941-5499
Ayguadé Parra, Eduard|||0000-0002-5146-103X
Valero Cortés, Mateo|||0000-0003-2917-2482
author2_role author
author
author
author
author
author
dc.subject.none.fl_str_mv Supercomputers
High performance computing
Parallel programming (Computer science)
Scheduling
Runtime systems
Asymmetric multi-cores
HPC
Superordinadors
Càlcul intensiu (Informàtica)
Programació en paral·lel (Informàtica)
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
topic Supercomputers
High performance computing
Parallel programming (Computer science)
Scheduling
Runtime systems
Asymmetric multi-cores
HPC
Superordinadors
Càlcul intensiu (Informàtica)
Programació en paral·lel (Informàtica)
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
description Asymmetric multi-cores (AMCs) are a successful architectural solution for both mobile devices and supercomputers. By maintaining two types of cores (fast and slow) AMCs are able to provide high performance under the facility power budget. This paper performs the first extensive evaluation of how portable are the current HPC applications for such supercomputing systems. Specifically we evaluate several execution models on an ARM big.LITTLE AMC using the PARSEC benchmark suite that includes representative highly parallel applications. We compare schedulers at the user, OS and runtime levels, using both static and dynamic options and multiple configurations, and assess the impact of these options on the well-known problem of balancing the load across AMCs. Our results demonstrate that scheduling is more effective when it takes place in the runtime system level as it improves the baseline by 23%, while the heterogeneous-aware OS scheduling solution improves the baseline by 10%.
publishDate 2019
dc.date.none.fl_str_mv 2019
2019-05-01
2019
2019-05-24
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
AM
http://purl.org/coar/version/c_ab4af688f83e57aa
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/133416
https://dx.doi.org/10.1016/j.jpdc.2019.01.007
url https://hdl.handle.net/2117/133416
https://dx.doi.org/10.1016/j.jpdc.2019.01.007
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.relation.none.fl_str_mv Ministerio de Economía y Competitividad http://doi.org/10.13039/501100003329 TIN2015-65316-P COMPUTACION DE ALTAS PRESTACIONES VII
European Commission http://dx.doi.org/10.13039/100011102 Seventh Framework Programme 321253 Riding on Moore's Law
European Commission http://doi.org/10.13039/100010661 Horizon 2020 Framework Programme 671697 Mont-Blanc 3, European scalable and power efficient HPC platform based on low-power embedded technology
European Commission http://doi.org/10.13039/100010661 Horizon 2020 Framework Programme 779877 Mont-Blanc 2020, European scalable, modular and power efficient HPC processor
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Elsevier
publisher.none.fl_str_mv Elsevier
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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