Modeling and optimization of timing interference for time critical systems on multicore COTS platforms
(English) Critical Real-Time Embedded Systems (CRTES) underpin automotive, aerospace, medical devices, among others. They must guarantee deterministic, certifiable behavior under worst-case conditions. As functionality grows (sensor fusion, AI, etc), uniprocessors fall short, prompting adoption of C...
| Autor: | |
|---|---|
| Tipo de recurso: | tesis doctoral |
| Fecha de publicación: | 2026 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/452436 |
| Acceso en línea: | https://hdl.handle.net/2117/452436 https://dx.doi.org/10.5821/dissertation-2117-452436 |
| Access Level: | acceso embargado |
| Palabra clave: | Hardware Event Monitors Timing Analysis Real-Time Embedded Systems Crossbar Contention Multicore System-on-Chip (SoC) Heterogeneous Memory Sequence-Aware Modeling Execution Traces Memory Hierarchy 004 - Informàtica Àrees temàtiques de la UPC::Informàtica |
| Sumario: | (English) Critical Real-Time Embedded Systems (CRTES) underpin automotive, aerospace, medical devices, among others. They must guarantee deterministic, certifiable behavior under worst-case conditions. As functionality grows (sensor fusion, AI, etc), uniprocessors fall short, prompting adoption of COTS multicores. Yet shared resources induce timing interference that threatens predictability and complicates certification, especially in heterogeneous SoCs with crossbars, bridges, and hierarchical memory. This Thesis advances timing predictability on complex multicores through three linked pillars: standardized hardware observability, contention modeling, and system-level optimization. Together they form a coherent, auditable path from low-level measurements to design decisions. First, we introduce unified observability frameworks combining core-local counters with system-level tracing. They correlate hardware events with task phases, reconstruct scheduling and contention across cores and interconnects, and standardize configuration and interpretation across heterogeneous devices. Measurements are attributed to tasks (excluding OS activity), incur bounded overhead, and yield ordered access sequences preserving temporal structure. Along with latency tables for memories and bridges, these artifacts make timing phenomena measurable and calibrate conservative models. Second, we develop contention models grounded in realistic traces. Traditional Access-Count Contention Techniques (ACCT) are overly conservative for parallel crossbars. Sequence-Aware Techniques (SACT) exploit request ordering to prune infeasible overlaps and tighten bounds. We propose ASCOM, a scalable framework balancing accuracy through compositional pairing against contender sequences and segmentation of long traces. We derive explicit upper/lower bounds to quantify margins and add bridge awareness to capture inter-cluster traversals and remote-memory asymmetries. Across single- and multi-crossbar SoCs, sequence-aware analysis yields tighter, trustworthy bounds while remaining tractable on industrial-scale traces. Third, we examine how modeling informs code and data placement across heterogeneous memories. Feasibility considers capacity and compatibility; locality and non-uniform latencies are captured through calibrated SACT. Exploration reveals pronounced sensitivity to placement: with identical workloads and schedules, changing only the mapping can shift contention by over 100% of reference execution time, due to bridge traversals, device asymmetries, and port effects. Architectural factors thus directly shape worst-case interference, elevating placement to a first-order design parameter. An end-to-end workflow operationalizes these ideas. System-level traces are captured on an industrial target hardware. Traces are filtered into ordered access sequences retaining temporal structure and feeding SACT analysis. Empirical campaigns build latency tables for memories and bridges. With these calibrated inputs, the bridge-aware SACT model estimates contention and total delay for alternative placements. Results show robust contention analysis on COTS multicores is feasible when: (i) the right signals are observed with standardized, low-intrusion instrumentation; (ii) models are sequence- and bridge-aware with explicit margins; and (iii) insights drive placement where locality and capacity are addressed coherently. Because ordered sequences, latency tables, and task-scoped metrics come from the deployed hardware, conclusions are auditable and fit safety cases. Combining hardware-aware instrumentation, realistic modeling, and contention-driven mapping, the Thesis provides a practical framework for timing predictability in CRTES and narrows the gap between certification expectations: traceability, explainability, repeatability and the behavior of parallel interconnects and heterogeneous memories in contemporary multicore SoCs. |
|---|