A case for resource-conscious out-of-order processors
Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed an...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2003 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/103112 |
| Acceso en línea: | https://hdl.handle.net/2117/103112 https://dx.doi.org/10.1109/L-CA.2003.4 |
| Access Level: | acceso abierto |
| Palabra clave: | Microprocessors -- Design and construction Out-of-order processor Memory latency Instruction-level parallelism Resource utilization Checkpointing Microprocessadors -- Disseny i construcció Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed and memory latency, tolerating upcoming latencies in this way would require impractical sizes of such critical resources.To tackle this scalability problem, we make a case for resource-conscious out-of-order processors. We present quantitative evidence that critical resources are increasingly underutilized in these processors. We advocate that better use of such resources should be a priority in future research in processor architectures. |
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