Architectural support for high-performing hardware transactional memory systems

Parallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes the development of parallel software a hard and errorprone task. In addition to th...

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Detalles Bibliográficos
Autor: Lupon Navazo, Marc
Tipo de recurso: tesis doctoral
Fecha de publicación:2011
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/94562
Acceso en línea:https://hdl.handle.net/2117/94562
https://dx.doi.org/10.5821/dissertation-2117-94562
Access Level:acceso abierto
Palabra clave:Hardware transactional memory
Parallel programming
Dynamically adaptive systems
Non-blocring synchronization
FASTM
DYNTM
SWPTM
208
Programació en paral·lel (Informàtica)
Sistemes adaptatius
Àrees temàtiques de la UPC::Informàtica
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dc.title.none.fl_str_mv Architectural support for high-performing hardware transactional memory systems
title Architectural support for high-performing hardware transactional memory systems
spellingShingle Architectural support for high-performing hardware transactional memory systems
Lupon Navazo, Marc
Hardware transactional memory
Parallel programming
Dynamically adaptive systems
Non-blocring synchronization
FASTM
DYNTM
SWPTM
208
Programació en paral·lel (Informàtica)
Sistemes adaptatius
Àrees temàtiques de la UPC::Informàtica
title_short Architectural support for high-performing hardware transactional memory systems
title_full Architectural support for high-performing hardware transactional memory systems
title_fullStr Architectural support for high-performing hardware transactional memory systems
title_full_unstemmed Architectural support for high-performing hardware transactional memory systems
title_sort Architectural support for high-performing hardware transactional memory systems
dc.creator.none.fl_str_mv Lupon Navazo, Marc
author Lupon Navazo, Marc
author_facet Lupon Navazo, Marc
author_role author
dc.contributor.none.fl_str_mv Magklis, Grigorios
González Colás, Antonio María
dc.subject.none.fl_str_mv Hardware transactional memory
Parallel programming
Dynamically adaptive systems
Non-blocring synchronization
FASTM
DYNTM
SWPTM
208
Programació en paral·lel (Informàtica)
Sistemes adaptatius
Àrees temàtiques de la UPC::Informàtica
topic Hardware transactional memory
Parallel programming
Dynamically adaptive systems
Non-blocring synchronization
FASTM
DYNTM
SWPTM
208
Programació en paral·lel (Informàtica)
Sistemes adaptatius
Àrees temàtiques de la UPC::Informàtica
description Parallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes the development of parallel software a hard and errorprone task. In addition to this, current synchronization techniques serialize the execution of those critical sections that conflict in shared memory and thus limit the scalability of multithreaded applications. Transactional Memory (TM) has emerged as a promising programming model that solves the trade-off between high performance and ease of use. In TM, the system is in charge of scheduling transactions (atomic blocks of instructions) and guaranteeing that they are executed in isolation, which simplifies writing parallel code and, at the same time, enables high concurrency when atomic regions access different data. Among all forms of TM environments, Hardware TM (HTM) systems is the only one that offers fast execution at the cost of adding dedicated logic in the processor. Existing HTMsystems suffer considerable delays when they execute complex transactional workloads, especially when they deal with large and contending transactions because they lack adaptability. Furthermore, most HTM implementations are ad hoc and require cumbersome hardware structures to be effective, which complicates the feasibility of the design. This thesis makes several contributions in the design and analysis of low-cost HTMsystems that yield good performance for any kind of TM program. Our first contribution, FASTM, introduces a novel mechanism to elegantly manage speculative (and already validated) versions of transactional data by slightly modifying on-chip memory engine. This approach permits fast recovery when a transaction that fits in private caches is discarded. At the same time, it keeps non-speculative values in software, which allows in-place x memory updates. Thus, FASTM is not hurt from capacity issues nor slows down when it has to undo transactional modifications. Our second contribution includes two different HTM systems that integrate deferred resolution of conflicts in a conventional multicore processor, which reduces the complexity of the system with respect to previous proposals. The first one, FUSETM, combines different-mode transactions under a unified infrastructure to gracefully handle resource overflow. As a result, FUSETM brings fast transactional computation without requiring additional hardware nor extra communication at the end of speculative execution. The second one, SPECTM, introduces a two-level data versioning mechanism to resolve conflicts in a speculative fashion even in the case of overflow. Our third and last contribution presents a couple of truly flexible HTM systems that can dynamically adapt their underlying mechanisms according to the characteristics of the program. DYNTM records statistics of previously executed transactions to select the best-suited strategy each time a new instance of a transaction starts. SWAPTM takes a different approach: it tracks information of the current transactional instance to change its priority level at runtime. Both alternatives obtain great performance over existing proposals that employ fixed transactional policies, especially in applications with phase changes.
publishDate 2011
dc.date.none.fl_str_mv 2011
2011-12-23
2012
2012-04-20
dc.type.none.fl_str_mv doctoral thesis
http://purl.org/coar/resource_type/c_db06
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/doctoralThesis
format doctoralThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/94562
https://dx.doi.org/10.5821/dissertation-2117-94562
url https://hdl.handle.net/2117/94562
https://dx.doi.org/10.5821/dissertation-2117-94562
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universitat Politècnica de Catalunya
publisher.none.fl_str_mv Universitat Politècnica de Catalunya
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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spelling Architectural support for high-performing hardware transactional memory systemsLupon Navazo, MarcHardware transactional memoryParallel programmingDynamically adaptive systemsNon-blocring synchronizationFASTMDYNTMSWPTM208Programació en paral·lel (Informàtica)Sistemes adaptatiusÀrees temàtiques de la UPC::InformàticaParallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes the development of parallel software a hard and errorprone task. In addition to this, current synchronization techniques serialize the execution of those critical sections that conflict in shared memory and thus limit the scalability of multithreaded applications. Transactional Memory (TM) has emerged as a promising programming model that solves the trade-off between high performance and ease of use. In TM, the system is in charge of scheduling transactions (atomic blocks of instructions) and guaranteeing that they are executed in isolation, which simplifies writing parallel code and, at the same time, enables high concurrency when atomic regions access different data. Among all forms of TM environments, Hardware TM (HTM) systems is the only one that offers fast execution at the cost of adding dedicated logic in the processor. Existing HTMsystems suffer considerable delays when they execute complex transactional workloads, especially when they deal with large and contending transactions because they lack adaptability. Furthermore, most HTM implementations are ad hoc and require cumbersome hardware structures to be effective, which complicates the feasibility of the design. This thesis makes several contributions in the design and analysis of low-cost HTMsystems that yield good performance for any kind of TM program. Our first contribution, FASTM, introduces a novel mechanism to elegantly manage speculative (and already validated) versions of transactional data by slightly modifying on-chip memory engine. This approach permits fast recovery when a transaction that fits in private caches is discarded. At the same time, it keeps non-speculative values in software, which allows in-place x memory updates. Thus, FASTM is not hurt from capacity issues nor slows down when it has to undo transactional modifications. Our second contribution includes two different HTM systems that integrate deferred resolution of conflicts in a conventional multicore processor, which reduces the complexity of the system with respect to previous proposals. The first one, FUSETM, combines different-mode transactions under a unified infrastructure to gracefully handle resource overflow. As a result, FUSETM brings fast transactional computation without requiring additional hardware nor extra communication at the end of speculative execution. The second one, SPECTM, introduces a two-level data versioning mechanism to resolve conflicts in a speculative fashion even in the case of overflow. Our third and last contribution presents a couple of truly flexible HTM systems that can dynamically adapt their underlying mechanisms according to the characteristics of the program. DYNTM records statistics of previously executed transactions to select the best-suited strategy each time a new instance of a transaction starts. SWAPTM takes a different approach: it tracks information of the current transactional instance to change its priority level at runtime. Both alternatives obtain great performance over existing proposals that employ fixed transactional policies, especially in applications with phase changes.Universitat Politècnica de CatalunyaMagklis, GrigoriosGonzález Colás, Antonio María20112011-12-2320122012-04-20doctoral thesishttp://purl.org/coar/resource_type/c_db06VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/doctoralThesisapplication/pdfhttps://hdl.handle.net/2117/94562https://dx.doi.org/10.5821/dissertation-2117-94562reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/945622026-05-27T15:37:01Z
score 15.300724

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