Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs

This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non f...

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Detalhes bibliográficos
Autores: Clemente Barreira, Juan Antonio, Mansour, Wassim, Ayoubi, Rafic, Serrano, Felipe, Mecha López, Hortensia, Ziade, Haissam, El Falou, Wassim, Velazco, Raoul
Formato: artículo
Fecha de publicación:2016
País:España
Recursos:Universidad Complutense de Madrid (UCM)
Repositorio:Docta Complutense
Idioma:inglés
OAI Identifier:oai:docta.ucm.es:20.500.14352/24602
Acesso em linha:https://hdl.handle.net/20.500.14352/24602
Access Level:acceso abierto
Palavra-chave:004.032.26
004.312
004.052.3
Artificial Neural Network (ANN)
Hopfield Neural Network (HNN)
Single Event Upset (SEU)
Single Event Transient (SET)
FPGA
Fault tolerance
Hardware
Descrição
Resumo:This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.

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