Evaluation and methods to increase efficiency of HPC systems with different maturity levels
(English) High-Performance Computing (HPC) has entered an era of increasing architectural diversity and complexity, with systems ranging from experimental prototypes to large-scale production machines. This evolution presents a fundamental challenge: how to consistently evaluate performance, scalabi...
| Autor: | |
|---|---|
| Tipo de recurso: | tesis doctoral |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/449863 |
| Acceso en línea: | https://hdl.handle.net/2117/449863 https://dx.doi.org/10.5821/dissertation-2117-449863 |
| Access Level: | acceso abierto |
| Palabra clave: | High-Performance Computing Benchmarking Performance Analysis Performance Models Efficiency Models Technology Readiness Levels Roofline Top-Down Software Development Vehicles x86 Arm Nvidia RISC-V 004 - Informàtica Àrees temàtiques de la UPC::Informàtica |
| Sumario: | (English) High-Performance Computing (HPC) has entered an era of increasing architectural diversity and complexity, with systems ranging from experimental prototypes to large-scale production machines. This evolution presents a fundamental challenge: how to consistently evaluate performance, scalability, and efficiency across platforms with varying levels of technological maturity. Traditional benchmarking methods, while effective for fully deployed systems, often fall short when applied to early-stage prototypes where software stacks are incomplete or hardware is still under development. This thesis proposes and develops a comprehensive evaluation methodology capable of addressing these challenges. The approach gives a multi-layered perspective on performance, and it is structured around three complementary levels: micro-benchmarks, standard HPC benchmarks, and full scientific applications. Technology Readiness Levels (TRLs) are introduced as a guiding concept, allowing the methodology to be adapted according to the maturity of the system under study. At high TRL, the methodology enables comparative assessments of production supercomputers, while at low TRL, it helps identify bottlenecks and optimization opportunities early in the design cycle. The thesis contributes both conceptual and practical tools. It formalizes performance and efficiency models (including Roofline, Top-Down, and efficiency metrics) and demonstrates their use across multiple architectures. It further extends tracing and monitoring capabilities for emerging processors, introduces methods to access and interpret hardware counters on novel architectures such as \riscv, and evaluates the integration of experimental hardware through Software Development Vehicles (SDVs) and FPGA-based emulation. These tools are validated through case studies on production systems, such as the MareNostrum 5 supercomputer and other HPC clusters deployed at the Barcelona Supercomputing Center (BSC), as well as on prototypes from European projects, such as EPAC. Results show that the proposed methodology provides actionable insights at all maturity levels: from guiding hardware-software co-design in early-stage processors to enabling reproducible performance comparisons across pre-exascale systems. Beyond benchmarking, it provides valuable feedback for hardware architects, system software developers, and application scientists alike. By bridging the gap between low-TRL prototypes and production-ready HPC systems, this work contributes to building a consistent framework for evaluating and improving the efficiency of future European and global supercomputers. |
|---|