Janus: an FPGA-based system for high-performance scientific computing

This paper describes JANUS, a modular massively parallel and reconfigurable FPGA-based computing system. Each JANUS module has a computational core and a host. The computational core is a 4x4 array of FPGA-based processing elements with nearest-neighbor data links. Processors are also directly conne...

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Detalles Bibliográficos
Autores: Fernández Pérez, Luis Antonio, Martín Mayor, Víctor, Muñoz Sudupe, Antonio, Yllanes, D., otros, ...
Tipo de recurso: artículo
Fecha de publicación:2009
País:España
Institución:Universidad Complutense de Madrid (UCM)
Repositorio:Docta Complutense
Idioma:inglés
OAI Identifier:oai:docta.ucm.es:20.500.14352/45073
Acceso en línea:https://hdl.handle.net/20.500.14352/45073
Access Level:acceso abierto
Palabra clave:53
51-73
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Física (Física)
Física-Modelos matemáticos
22 Física
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spelling Janus: an FPGA-based system for high-performance scientific computingFernández Pérez, Luis AntonioMartín Mayor, VíctorMuñoz Sudupe, AntonioYllanes, D.otros, ...5351-73ImpuritiesIanus.Física (Física)Física-Modelos matemáticos22 FísicaThis paper describes JANUS, a modular massively parallel and reconfigurable FPGA-based computing system. Each JANUS module has a computational core and a host. The computational core is a 4x4 array of FPGA-based processing elements with nearest-neighbor data links. Processors are also directly connected to an I/O node attached to the JANUS host, a conventional PC. JANUS is tailored for, but not limited to, the requirements of a class of hard scientific applications characterized by regular code structure, unconventional data manipulation instructions and not too large data-base size. We discuss the architecture of this configurable machine, and focus on its use on Monte Carlo simulations of statistical mechanics. On this class of application JANUS achieves impressive performances: in some cases one JANUS processing element outperfoms high-end PCs by a factor ≈1000. We also discuss the role of JANUS on other classes of scientific applications.IEEE Computer Soc.Universidad Complutense de Madrid20092009-01-0120092009-01-01journal articlehttp://purl.org/coar/resource_type/c_6501info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/20.500.14352/45073reponame:Docta Complutenseinstname:Universidad Complutense de Madrid (UCM)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:docta.ucm.es:20.500.14352/450732026-06-02T12:44:21Z
dc.title.none.fl_str_mv Janus: an FPGA-based system for high-performance scientific computing
title Janus: an FPGA-based system for high-performance scientific computing
spellingShingle Janus: an FPGA-based system for high-performance scientific computing
Fernández Pérez, Luis Antonio
53
51-73
Impurities
Ianus.
Física (Física)
Física-Modelos matemáticos
22 Física
title_short Janus: an FPGA-based system for high-performance scientific computing
title_full Janus: an FPGA-based system for high-performance scientific computing
title_fullStr Janus: an FPGA-based system for high-performance scientific computing
title_full_unstemmed Janus: an FPGA-based system for high-performance scientific computing
title_sort Janus: an FPGA-based system for high-performance scientific computing
dc.creator.none.fl_str_mv Fernández Pérez, Luis Antonio
Martín Mayor, Víctor
Muñoz Sudupe, Antonio
Yllanes, D.
otros, ...
author Fernández Pérez, Luis Antonio
author_facet Fernández Pérez, Luis Antonio
Martín Mayor, Víctor
Muñoz Sudupe, Antonio
Yllanes, D.
otros, ...
author_role author
author2 Martín Mayor, Víctor
Muñoz Sudupe, Antonio
Yllanes, D.
otros, ...
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Universidad Complutense de Madrid
dc.subject.none.fl_str_mv 53
51-73
Impurities
Ianus.
Física (Física)
Física-Modelos matemáticos
22 Física
topic 53
51-73
Impurities
Ianus.
Física (Física)
Física-Modelos matemáticos
22 Física
description This paper describes JANUS, a modular massively parallel and reconfigurable FPGA-based computing system. Each JANUS module has a computational core and a host. The computational core is a 4x4 array of FPGA-based processing elements with nearest-neighbor data links. Processors are also directly connected to an I/O node attached to the JANUS host, a conventional PC. JANUS is tailored for, but not limited to, the requirements of a class of hard scientific applications characterized by regular code structure, unconventional data manipulation instructions and not too large data-base size. We discuss the architecture of this configurable machine, and focus on its use on Monte Carlo simulations of statistical mechanics. On this class of application JANUS achieves impressive performances: in some cases one JANUS processing element outperfoms high-end PCs by a factor ≈1000. We also discuss the role of JANUS on other classes of scientific applications.
publishDate 2009
dc.date.none.fl_str_mv 2009
2009-01-01
2009
2009-01-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/20.500.14352/45073
url https://hdl.handle.net/20.500.14352/45073
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv IEEE Computer Soc.
publisher.none.fl_str_mv IEEE Computer Soc.
dc.source.none.fl_str_mv reponame:Docta Complutense
instname:Universidad Complutense de Madrid (UCM)
instname_str Universidad Complutense de Madrid (UCM)
reponame_str Docta Complutense
collection Docta Complutense
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300724