A Hybrid CMOS-Memristor Neuromorphic Synapse

Although data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper...

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Detalhes bibliográficos
Autores: Azghadi, Mostafa, R., Linares-Barranco, Bernabé, Abbott, Derek, Leong, Philip H.W.
Formato: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2017
País:España
Recursos:Consejo Superior de Investigaciones Científicas (CSIC)
Repositorio:DIGITAL.CSIC. Repositorio Institucional del CSIC
OAI Identifier:oai:digital.csic.es:10261/157615
Acesso em linha:http://hdl.handle.net/10261/157615
Access Level:acceso abierto
Palavra-chave:Synaptic Plasticity
Quadruplet
Triplet
STDP
Crossbar
Memristor
Neuromorphic
Learning
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spelling A Hybrid CMOS-Memristor Neuromorphic SynapseAzghadi, Mostafa, R.Linares-Barranco, BernabéAbbott, DerekLeong, Philip H.W.Synaptic PlasticityQuadrupletTripletSTDPCrossbarMemristorNeuromorphicLearningAlthough data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper proposes a high-performance nano-scale Complementary Metal Oxide Semiconductor (CMOS)-memristive circuit, which mimics a number of essential learning properties of biological synapses. The proposed synaptic circuit that is composed of memristors and CMOS transistors, alters its memristance in response to timing differences among its pre-and post-synaptic action potentials, giving rise to a family of Spike Timing Dependent Plasticity (STDP). The presented design advances preceding memristive synapse designs with regards to the ability to replicate essential behaviours characterised in a number of electrophysiological experiments performed in the animal brain, which involve higher order spike interactions. Furthermore, the proposed hybrid device CMOS area is estimated as 600μm in a 0.35μm process-this represents a factor of ten reduction in area with respect to prior CMOS art. The new design is integrated with silicon neurons in a crossbar array structure amenable to large-scale neuromorphic architectures and may pave the way for future neuromorphic systems with spike timing-dependent learning features. These systems are emerging for deployment in various applications ranging from basic neuroscience research, to pattern recognition, to Brain-Machine-Interfaces.Peer ReviewedInstitute of Electrical and Electronics EngineersConsejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]2017201720172017info:eu-repo/semantics/articlehttp://purl.org/coar/resource_type/c_6501Postprintinfo:eu-repo/semantics/acceptedVersionhttp://hdl.handle.net/10261/157615reponame:DIGITAL.CSIC. Repositorio Institucional del CSICinstname:Consejo Superior de Investigaciones Científicas (CSIC)InglésSíinfo:eu-repo/semantics/openAccessoai:digital.csic.es:10261/1576152026-05-22T06:33:51Z
dc.title.none.fl_str_mv A Hybrid CMOS-Memristor Neuromorphic Synapse
title A Hybrid CMOS-Memristor Neuromorphic Synapse
spellingShingle A Hybrid CMOS-Memristor Neuromorphic Synapse
Azghadi, Mostafa, R.
Synaptic Plasticity
Quadruplet
Triplet
STDP
Crossbar
Memristor
Neuromorphic
Learning
title_short A Hybrid CMOS-Memristor Neuromorphic Synapse
title_full A Hybrid CMOS-Memristor Neuromorphic Synapse
title_fullStr A Hybrid CMOS-Memristor Neuromorphic Synapse
title_full_unstemmed A Hybrid CMOS-Memristor Neuromorphic Synapse
title_sort A Hybrid CMOS-Memristor Neuromorphic Synapse
dc.creator.none.fl_str_mv Azghadi, Mostafa, R.
Linares-Barranco, Bernabé
Abbott, Derek
Leong, Philip H.W.
author Azghadi, Mostafa, R.
author_facet Azghadi, Mostafa, R.
Linares-Barranco, Bernabé
Abbott, Derek
Leong, Philip H.W.
author_role author
author2 Linares-Barranco, Bernabé
Abbott, Derek
Leong, Philip H.W.
author2_role author
author
author
dc.contributor.none.fl_str_mv Consejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]
dc.subject.none.fl_str_mv Synaptic Plasticity
Quadruplet
Triplet
STDP
Crossbar
Memristor
Neuromorphic
Learning
topic Synaptic Plasticity
Quadruplet
Triplet
STDP
Crossbar
Memristor
Neuromorphic
Learning
description Although data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper proposes a high-performance nano-scale Complementary Metal Oxide Semiconductor (CMOS)-memristive circuit, which mimics a number of essential learning properties of biological synapses. The proposed synaptic circuit that is composed of memristors and CMOS transistors, alters its memristance in response to timing differences among its pre-and post-synaptic action potentials, giving rise to a family of Spike Timing Dependent Plasticity (STDP). The presented design advances preceding memristive synapse designs with regards to the ability to replicate essential behaviours characterised in a number of electrophysiological experiments performed in the animal brain, which involve higher order spike interactions. Furthermore, the proposed hybrid device CMOS area is estimated as 600μm in a 0.35μm process-this represents a factor of ten reduction in area with respect to prior CMOS art. The new design is integrated with silicon neurons in a crossbar array structure amenable to large-scale neuromorphic architectures and may pave the way for future neuromorphic systems with spike timing-dependent learning features. These systems are emerging for deployment in various applications ranging from basic neuroscience research, to pattern recognition, to Brain-Machine-Interfaces.
publishDate 2017
dc.date.none.fl_str_mv 2017
2017
2017
2017
dc.type.none.fl_str_mv info:eu-repo/semantics/article
http://purl.org/coar/resource_type/c_6501
Postprint
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/10261/157615
url http://hdl.handle.net/10261/157615
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv Sí
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
dc.source.none.fl_str_mv reponame:DIGITAL.CSIC. Repositorio Institucional del CSIC
instname:Consejo Superior de Investigaciones Científicas (CSIC)
instname_str Consejo Superior de Investigaciones Científicas (CSIC)
reponame_str DIGITAL.CSIC. Repositorio Institucional del CSIC
collection DIGITAL.CSIC. Repositorio Institucional del CSIC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.198674

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