A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach

This paper presents a new architecture, design flow, and field-programmable gate array (FPGA) implementation analysis of a neuromorphic binaural auditory sensor, designed completely in the spike domain. Unlike digital cochleae that decompose audio signals using classical digital signal processing te...

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Autores: Jiménez Fernández, Ángel Francisco, Cerezuela Escudero, Elena, Miró Amarante, María Lourdes, Domínguez Morales, Manuel Jesús, Gómez Rodríguez, Francisco de Asís, Linares Barranco, Alejandro, Jiménez Moreno, Gabriel
Tipo de documento: artigo
Estado:Versión enviada para evaluación y publicación
Data de publicação:2017
País:España
Recursos:Universidad de Sevilla (US)
Repositório:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/87909
Acesso em linha:https://hdl.handle.net/11441/87909
https://doi.org/10.1109/TNNLS.2016.2583223
Access Level:Acceso aberto
Palavra-chave:Address event
Artificial cochlea
FPGA
Neuromorphic engineering
Pulse frequency modulation (PFM)
Real-time audition
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spelling A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing ApproachJiménez Fernández, Ángel FranciscoCerezuela Escudero, ElenaMiró Amarante, María LourdesDomínguez Morales, Manuel JesúsGómez Rodríguez, Francisco de AsísLinares Barranco, AlejandroJiménez Moreno, GabrielAddress eventArtificial cochleaFPGANeuromorphic engineeringPulse frequency modulation (PFM)Real-time auditionThis paper presents a new architecture, design flow, and field-programmable gate array (FPGA) implementation analysis of a neuromorphic binaural auditory sensor, designed completely in the spike domain. Unlike digital cochleae that decompose audio signals using classical digital signal processing techniques, the model presented in this paper processes information directly encoded as spikes using pulse frequency modulation and provides a set of frequency-decomposed audio information using an address-event representation interface. In this case, a systematic approach to design led to a generic process for building, tuning, and implementing audio frequency decomposers with different features, facilitating synthesis with custom features. This allows researchers to implement their own parameterized neuromorphic auditory systems in a low-cost FPGA in order to study the audio processing and learning activity that takes place in the brain. In this paper, we present a 64-channel binaural neuromorphic auditory system implemented in a Virtex-5 FPGA using a commercial development board. The system was excited with a diverse set of audio signals in order to analyze its response and characterize its features. The neuromorphic auditory system response times and frequencies are reported. The experimental results of the proposed system implementation with 64-channel stereo are: a frequency range between 9.6 Hz and 14.6 kHz (adjustable), a maximum output event rate of 2.19 Mevents/s, a power consumption of 29.7 mW, the slices requirements of 11 141, and a system clock frequency of 27 MHz.Ministerio de Economía y Competitividad TEC2012-37868-C04-02Junta de Andalucía P12-TIC-1300IEEE Computer SocietyArquitectura y Tecnología de ComputadoresTEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación2017info:eu-repo/semantics/articleinfo:eu-repo/semantics/submittedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/87909https://doi.org/10.1109/TNNLS.2016.2583223reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésIEEE Transactions on Neural Networks and Learning Systems, 28 (4), 804-818.TEC2012-37868-C04-02P12-TIC-1300https://ieeexplore.ieee.org/document/7523402info:eu-repo/semantics/openAccessoai:idus.us.es:11441/879092026-06-17T12:51:07Z
dc.title.none.fl_str_mv A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
title A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
spellingShingle A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
Jiménez Fernández, Ángel Francisco
Address event
Artificial cochlea
FPGA
Neuromorphic engineering
Pulse frequency modulation (PFM)
Real-time audition
title_short A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
title_full A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
title_fullStr A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
title_full_unstemmed A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
title_sort A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
dc.creator.none.fl_str_mv Jiménez Fernández, Ángel Francisco
Cerezuela Escudero, Elena
Miró Amarante, María Lourdes
Domínguez Morales, Manuel Jesús
Gómez Rodríguez, Francisco de Asís
Linares Barranco, Alejandro
Jiménez Moreno, Gabriel
author Jiménez Fernández, Ángel Francisco
author_facet Jiménez Fernández, Ángel Francisco
Cerezuela Escudero, Elena
Miró Amarante, María Lourdes
Domínguez Morales, Manuel Jesús
Gómez Rodríguez, Francisco de Asís
Linares Barranco, Alejandro
Jiménez Moreno, Gabriel
author_role author
author2 Cerezuela Escudero, Elena
Miró Amarante, María Lourdes
Domínguez Morales, Manuel Jesús
Gómez Rodríguez, Francisco de Asís
Linares Barranco, Alejandro
Jiménez Moreno, Gabriel
author2_role author
author
author
author
author
author
dc.contributor.none.fl_str_mv Arquitectura y Tecnología de Computadores
TEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación
dc.subject.none.fl_str_mv Address event
Artificial cochlea
FPGA
Neuromorphic engineering
Pulse frequency modulation (PFM)
Real-time audition
topic Address event
Artificial cochlea
FPGA
Neuromorphic engineering
Pulse frequency modulation (PFM)
Real-time audition
description This paper presents a new architecture, design flow, and field-programmable gate array (FPGA) implementation analysis of a neuromorphic binaural auditory sensor, designed completely in the spike domain. Unlike digital cochleae that decompose audio signals using classical digital signal processing techniques, the model presented in this paper processes information directly encoded as spikes using pulse frequency modulation and provides a set of frequency-decomposed audio information using an address-event representation interface. In this case, a systematic approach to design led to a generic process for building, tuning, and implementing audio frequency decomposers with different features, facilitating synthesis with custom features. This allows researchers to implement their own parameterized neuromorphic auditory systems in a low-cost FPGA in order to study the audio processing and learning activity that takes place in the brain. In this paper, we present a 64-channel binaural neuromorphic auditory system implemented in a Virtex-5 FPGA using a commercial development board. The system was excited with a diverse set of audio signals in order to analyze its response and characterize its features. The neuromorphic auditory system response times and frequencies are reported. The experimental results of the proposed system implementation with 64-channel stereo are: a frequency range between 9.6 Hz and 14.6 kHz (adjustable), a maximum output event rate of 2.19 Mevents/s, a power consumption of 29.7 mW, the slices requirements of 11 141, and a system clock frequency of 27 MHz.
publishDate 2017
dc.date.none.fl_str_mv 2017
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/submittedVersion
format article
status_str submittedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/87909
https://doi.org/10.1109/TNNLS.2016.2583223
url https://hdl.handle.net/11441/87909
https://doi.org/10.1109/TNNLS.2016.2583223
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv IEEE Transactions on Neural Networks and Learning Systems, 28 (4), 804-818.
TEC2012-37868-C04-02
P12-TIC-1300
https://ieeexplore.ieee.org/document/7523402
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv IEEE Computer Society
publisher.none.fl_str_mv IEEE Computer Society
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300724

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