A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-μm fully...

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Detalles Bibliográficos
Autores: Liñán Cembrano, Gustavo, Rodríguez Vázquez, Ángel Benito, Carmona Galán, Ricardo, Jiménez Garrido, Francisco José, Espejo Meana, Servando Carlos, Domínguez Castro, Rafael
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2004
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/76228
Acceso en línea:https://hdl.handle.net/11441/76228
https://doi.org/10.1109/JSSC.2004.829931
Access Level:acceso abierto
Palabra clave:Focal plane array processors
Mixed-signal SIMD vision chips
Visual microprocessors
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spelling A 1000 FPS at 128×128 vision processor with 8-bit digitized I/OLiñán Cembrano, GustavoRodríguez Vázquez, Ángel BenitoCarmona Galán, RicardoJiménez Garrido, Francisco JoséEspejo Meana, Servando CarlosDomínguez Castro, RafaelFocal plane array processorsMixed-signal SIMD vision chipsVisual microprocessorsThis paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-μm fully digital CMOS technology, contains ∼ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm2 and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 μs have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.European Commission IST-2001-38097Office of Naval Research (USA) N000140210884Institute of Electrical and Electronics EngineersElectrónica y ElectromagnetismoEuropean Commission (EC)Office of Naval Research (ONR). United States2004info:eu-repo/semantics/articleinfo:eu-repo/semantics/acceptedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/76228https://doi.org/10.1109/JSSC.2004.829931reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésIEEE Journal of Solid-State Circuits, 39 (7), 1044-1055.IST-2001-38097N000140210884http://dx.doi.org/10.1109/JSSC.2004.829931info:eu-repo/semantics/openAccessoai:idus.us.es:11441/762282026-06-17T12:51:07Z
dc.title.none.fl_str_mv A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
title A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
spellingShingle A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
Liñán Cembrano, Gustavo
Focal plane array processors
Mixed-signal SIMD vision chips
Visual microprocessors
title_short A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
title_full A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
title_fullStr A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
title_full_unstemmed A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
title_sort A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
dc.creator.none.fl_str_mv Liñán Cembrano, Gustavo
Rodríguez Vázquez, Ángel Benito
Carmona Galán, Ricardo
Jiménez Garrido, Francisco José
Espejo Meana, Servando Carlos
Domínguez Castro, Rafael
author Liñán Cembrano, Gustavo
author_facet Liñán Cembrano, Gustavo
Rodríguez Vázquez, Ángel Benito
Carmona Galán, Ricardo
Jiménez Garrido, Francisco José
Espejo Meana, Servando Carlos
Domínguez Castro, Rafael
author_role author
author2 Rodríguez Vázquez, Ángel Benito
Carmona Galán, Ricardo
Jiménez Garrido, Francisco José
Espejo Meana, Servando Carlos
Domínguez Castro, Rafael
author2_role author
author
author
author
author
dc.contributor.none.fl_str_mv Electrónica y Electromagnetismo
European Commission (EC)
Office of Naval Research (ONR). United States
dc.subject.none.fl_str_mv Focal plane array processors
Mixed-signal SIMD vision chips
Visual microprocessors
topic Focal plane array processors
Mixed-signal SIMD vision chips
Visual microprocessors
description This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-μm fully digital CMOS technology, contains ∼ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm2 and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 μs have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.
publishDate 2004
dc.date.none.fl_str_mv 2004
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/76228
https://doi.org/10.1109/JSSC.2004.829931
url https://hdl.handle.net/11441/76228
https://doi.org/10.1109/JSSC.2004.829931
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv IEEE Journal of Solid-State Circuits, 39 (7), 1044-1055.
IST-2001-38097
N000140210884
http://dx.doi.org/10.1109/JSSC.2004.829931
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,301603

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