A highly scalable parallel implementation of H.264
Developing parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation of H.264 that scales to a large number of cores. The algorithm exploits th...
| Autores: | , , , , , , , |
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| Tipo de documento: | artigo |
| Data de publicação: | 2011 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositório: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglês |
| OAI Identifier: | oai:upcommons.upc.edu:2117/106197 |
| Acesso em linha: | https://hdl.handle.net/2117/106197 https://dx.doi.org/10.1007/978-3-642-24568-8_6 |
| Access Level: | Acceso aberto |
| Palavra-chave: | Parallel processing (Electronic computers) Embedded computer systems Multiprocessors Embedded systems Entropy Multiprocessing systems Multithreading Parallel architectures Processor scheduling Video coding Processament en paral·lel (Ordinadors) Ordinadors immersos, Sistemes d' Multiprocessadors Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Resumo: | Developing parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation of H.264 that scales to a large number of cores. The algorithm exploits the fact that independent macroblocks (MBs) can be processed in parallel, but whereas a previous approach exploits only intra-frame MB-level parallelism, our algorithm exploits intra-frame as well as inter-frame MB-level parallelism. It is based on the observation that inter-frame dependencies have a limited spatial range. The algorithm has been implemented on a many-core architecture consisting of NXP TriMedia TM3270 embedded processors. This required to develop a subscription mechanism, where MBs are subscribed to the kick-off lists associated with the reference MBs. Extensive simulation results show that the implementation scales very well, achieving a speedup of more than 54 on a 64-core processor, in which case the previous approach achieves a speedup of only 23. Potential drawbacks of the 3D-Wave strategy are that the memory requirements increase since there can be many frames in flight, and that the frame latency might increase. Scheduling policies to address these drawbacks are also presented. The results show that these policies combat memory and latency issues with a negligible effect on the performance scalability. Results analyzing the impact of the memory latency, L1 cache size, and the synchronization and thread management overhead are also presented. Finally, we present performance requirements for entropy (CABAC) decoding. This work was performed while the fourth author was with NXP Semiconductors. |
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