Partitioning: an essential step in mapping algorithms into systolic array processors
The efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into subproblems that fit the array size.
| Autores: | , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 1987 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/105725 |
| Acceso en línea: | https://hdl.handle.net/2117/105725 https://dx.doi.org/10.1109/MC.1987.1663622 |
| Access Level: | acceso abierto |
| Palabra clave: | Systolic array circuits Partitioning algorithms Systolic arrays Signal processing algorithms Equations Fault tolerant systems Computational modeling Design methodology Hardware Digital signal processing Algorithm design and analysis Processadors de matrius (arrays) Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal |
| Sumario: | The efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into subproblems that fit the array size. |
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