Efficient hardware-in-the-loop models using automatic code generation with MATLAB/Simulink

Hardware-in-the-loop testing is usually a part of the design cycle of control systems. Efficient and fast models can be created in a Hardware Description Language (HDL), which is implemented in a Field-Programmable Gate Array (FPGA). Control engineers are more skilled in higher-level approaches. HDL...

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Detalles Bibliográficos
Autores: Saralegui, Roberto, Sánchez González, Alberto, Castro Martín, Ángel de
Tipo de recurso: artículo
Fecha de publicación:2023
País:España
Institución:Universidad Autónoma de Madrid
Repositorio:Biblos-e Archivo. Repositorio Institucional de la UAM
Idioma:inglés
OAI Identifier:oai:repositorio.uam.es:10486/711631
Acceso en línea:http://hdl.handle.net/10486/711631
https://dx.doi.org/10.3390/electronics12132786
Access Level:acceso abierto
Palabra clave:field-programmable gate array
hardware-in-the-loop
MATLAB
power converters
Simulink
Telecomunicaciones
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spelling Efficient hardware-in-the-loop models using automatic code generation with MATLAB/SimulinkSaralegui, RobertoSánchez González, AlbertoCastro Martín, Ángel defield-programmable gate arrayhardware-in-the-loopMATLABpower convertersSimulinkTelecomunicacionesHardware-in-the-loop testing is usually a part of the design cycle of control systems. Efficient and fast models can be created in a Hardware Description Language (HDL), which is implemented in a Field-Programmable Gate Array (FPGA). Control engineers are more skilled in higher-level approaches. HDL models derived automatically from schematics have noticeably lower performance, while HDL models derived from their equations are faster and smaller. However, even models translated automatically into HDL using the equations might be worse than manually coded models. A design workflow is proposed to achieve manual-like performance with automatic tools. It consists of the identification of similar operations, forcing signal signedness, and adjusting to multiplier input sizes. A detailed comparison was performed between three workflows: (1) translation of high-level MATLAB code, (2) translation of a Simulink model, and (3) working directly in the HDL. Sources of inefficiency were shown in a buck converter, and the process was validated in a full-bridge with electrical losses using a Runge–Kutta method. The results showed that the proposed approach delivered code that performed very close to a reference VHDL implementation, even for complex designs. Finally, the model was implemented in an off-the-shelf FPGA board suitable for a hardware-in-the-loop test setupThis work was supported by the Madrid Government (Comunidad de Madrid-Spain) under the Multiannual Agreement with Universidad Autónoma de Madrid in the line for the Excellence of the Universitary Teaching Staff, in the context of the V PRICIT (Regional Programme of Research and Technological Innovation)MDPIDepartamento de Tecnología Electrónica y de las ComunicacionesEscuela Politécnica Superior20232023-07-23research articlehttp://purl.org/coar/resource_type/c_2df8fbb1VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10486/711631https://dx.doi.org/10.3390/electronics12132786reponame:Biblos-e Archivo. Repositorio Institucional de la UAMinstname:Universidad Autónoma de MadridInglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:repositorio.uam.es:10486/7116312026-06-23T12:46:27Z
dc.title.none.fl_str_mv Efficient hardware-in-the-loop models using automatic code generation with MATLAB/Simulink
title Efficient hardware-in-the-loop models using automatic code generation with MATLAB/Simulink
spellingShingle Efficient hardware-in-the-loop models using automatic code generation with MATLAB/Simulink
Saralegui, Roberto
field-programmable gate array
hardware-in-the-loop
MATLAB
power converters
Simulink
Telecomunicaciones
title_short Efficient hardware-in-the-loop models using automatic code generation with MATLAB/Simulink
title_full Efficient hardware-in-the-loop models using automatic code generation with MATLAB/Simulink
title_fullStr Efficient hardware-in-the-loop models using automatic code generation with MATLAB/Simulink
title_full_unstemmed Efficient hardware-in-the-loop models using automatic code generation with MATLAB/Simulink
title_sort Efficient hardware-in-the-loop models using automatic code generation with MATLAB/Simulink
dc.creator.none.fl_str_mv Saralegui, Roberto
Sánchez González, Alberto
Castro Martín, Ángel de
author Saralegui, Roberto
author_facet Saralegui, Roberto
Sánchez González, Alberto
Castro Martín, Ángel de
author_role author
author2 Sánchez González, Alberto
Castro Martín, Ángel de
author2_role author
author
dc.contributor.none.fl_str_mv Departamento de Tecnología Electrónica y de las Comunicaciones
Escuela Politécnica Superior
dc.subject.none.fl_str_mv field-programmable gate array
hardware-in-the-loop
MATLAB
power converters
Simulink
Telecomunicaciones
topic field-programmable gate array
hardware-in-the-loop
MATLAB
power converters
Simulink
Telecomunicaciones
description Hardware-in-the-loop testing is usually a part of the design cycle of control systems. Efficient and fast models can be created in a Hardware Description Language (HDL), which is implemented in a Field-Programmable Gate Array (FPGA). Control engineers are more skilled in higher-level approaches. HDL models derived automatically from schematics have noticeably lower performance, while HDL models derived from their equations are faster and smaller. However, even models translated automatically into HDL using the equations might be worse than manually coded models. A design workflow is proposed to achieve manual-like performance with automatic tools. It consists of the identification of similar operations, forcing signal signedness, and adjusting to multiplier input sizes. A detailed comparison was performed between three workflows: (1) translation of high-level MATLAB code, (2) translation of a Simulink model, and (3) working directly in the HDL. Sources of inefficiency were shown in a buck converter, and the process was validated in a full-bridge with electrical losses using a Runge–Kutta method. The results showed that the proposed approach delivered code that performed very close to a reference VHDL implementation, even for complex designs. Finally, the model was implemented in an off-the-shelf FPGA board suitable for a hardware-in-the-loop test setup
publishDate 2023
dc.date.none.fl_str_mv 2023
2023-07-23
dc.type.none.fl_str_mv research article
http://purl.org/coar/resource_type/c_2df8fbb1
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv http://hdl.handle.net/10486/711631
https://dx.doi.org/10.3390/electronics12132786
url http://hdl.handle.net/10486/711631
https://dx.doi.org/10.3390/electronics12132786
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv MDPI
publisher.none.fl_str_mv MDPI
dc.source.none.fl_str_mv reponame:Biblos-e Archivo. Repositorio Institucional de la UAM
instname:Universidad Autónoma de Madrid
instname_str Universidad Autónoma de Madrid
reponame_str Biblos-e Archivo. Repositorio Institucional de la UAM
collection Biblos-e Archivo. Repositorio Institucional de la UAM
repository.name.fl_str_mv
repository.mail.fl_str_mv
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