Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters
This paper presents a toolbox for the time-domain simulation and optimization-based high-level synthesis of pipeline analog-to-digital converters in MATLAB®. Behavioral models of building blocks, including their critical error mechanisms, are described and incorporated into SIMULINK® as C-compiled S...
| Autores: | , , |
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| Tipo de documento: | artigo |
| Data de publicação: | 2004 |
| País: | España |
| Recursos: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repositório: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/3843 |
| Acesso em linha: | http://hdl.handle.net/10261/3843 |
| Access Level: | Acceso aberto |
| Palavra-chave: | Pipeline Analog-to-Digital Converters High-level Synthesis |
| Resumo: | This paper presents a toolbox for the time-domain simulation and optimization-based high-level synthesis of pipeline analog-to-digital converters in MATLAB®. Behavioral models of building blocks, including their critical error mechanisms, are described and incorporated into SIMULINK® as C-compiled S-functions. This approach significantly speeds up system-level simulations while keeping high accuracy −verified with HSPICE− and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable alternative for the design of broadband communication analog front-ends. As a case study, an embedded 0.13μm CMOS 12bit@80MS/s ADC for a PLC chipset is designed to show the capabilities of the presented tool. |
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