Architectural support for high-performing hardware transactional memory systems
Parallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes the development of parallel software a hard and errorprone task. In addition to th...
| Autor: | |
|---|---|
| Formato: | tesis doctoral |
| Estado: | Versión publicada |
| Fecha de publicación: | 2011 |
| País: | España |
| Recursos: | CBUC, CESCA |
| Repositorio: | TDR. Tesis Doctorales en Red |
| OAI Identifier: | oai:www.tdx.cat:10803/80383 |
| Acesso em linha: | http://hdl.handle.net/10803/80383 https://dx.doi.org/10.5821/dissertation-2117-94562 |
| Access Level: | acceso abierto |
| Palavra-chave: | Hardware transactional memory Parallel programming Dynamically adaptive systems Non-blocring synchronization FASTM DYNTM SWPTM 208 004 |
| id |
ES_738190f11b4fa96bced63b2aace62cb6 |
|---|---|
| oai_identifier_str |
oai:www.tdx.cat:10803/80383 |
| network_acronym_str |
ES |
| network_name_str |
España |
| repository_id_str |
|
| dc.title.none.fl_str_mv |
Architectural support for high-performing hardware transactional memory systems |
| title |
Architectural support for high-performing hardware transactional memory systems |
| spellingShingle |
Architectural support for high-performing hardware transactional memory systems Lupon Navazo, Marc Hardware transactional memory Parallel programming Dynamically adaptive systems Non-blocring synchronization FASTM DYNTM SWPTM 208 004 |
| title_short |
Architectural support for high-performing hardware transactional memory systems |
| title_full |
Architectural support for high-performing hardware transactional memory systems |
| title_fullStr |
Architectural support for high-performing hardware transactional memory systems |
| title_full_unstemmed |
Architectural support for high-performing hardware transactional memory systems |
| title_sort |
Architectural support for high-performing hardware transactional memory systems |
| dc.creator.none.fl_str_mv |
Lupon Navazo, Marc |
| author |
Lupon Navazo, Marc |
| author_facet |
Lupon Navazo, Marc |
| author_role |
author |
| dc.contributor.none.fl_str_mv |
Magklis, Grigorios González Colás, Antonio Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.subject.none.fl_str_mv |
Hardware transactional memory Parallel programming Dynamically adaptive systems Non-blocring synchronization FASTM DYNTM SWPTM 208 004 |
| topic |
Hardware transactional memory Parallel programming Dynamically adaptive systems Non-blocring synchronization FASTM DYNTM SWPTM 208 004 |
| description |
Parallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes the development of parallel software a hard and errorprone task. In addition to this, current synchronization techniques serialize the execution of those critical sections that conflict in shared memory and thus limit the scalability of multithreaded applications. Transactional Memory (TM) has emerged as a promising programming model that solves the trade-off between high performance and ease of use. In TM, the system is in charge of scheduling transactions (atomic blocks of instructions) and guaranteeing that they are executed in isolation, which simplifies writing parallel code and, at the same time, enables high concurrency when atomic regions access different data. Among all forms of TM environments, Hardware TM (HTM) systems is the only one that offers fast execution at the cost of adding dedicated logic in the processor. Existing HTMsystems suffer considerable delays when they execute complex transactional workloads, especially when they deal with large and contending transactions because they lack adaptability. Furthermore, most HTM implementations are ad hoc and require cumbersome hardware structures to be effective, which complicates the feasibility of the design. This thesis makes several contributions in the design and analysis of low-cost HTMsystems that yield good performance for any kind of TM program. Our first contribution, FASTM, introduces a novel mechanism to elegantly manage speculative (and already validated) versions of transactional data by slightly modifying on-chip memory engine. This approach permits fast recovery when a transaction that fits in private caches is discarded. At the same time, it keeps non-speculative values in software, which allows in-place x memory updates. Thus, FASTM is not hurt from capacity issues nor slows down when it has to undo transactional modifications. Our second contribution includes two different HTM systems that integrate deferred resolution of conflicts in a conventional multicore processor, which reduces the complexity of the system with respect to previous proposals. The first one, FUSETM, combines different-mode transactions under a unified infrastructure to gracefully handle resource overflow. As a result, FUSETM brings fast transactional computation without requiring additional hardware nor extra communication at the end of speculative execution. The second one, SPECTM, introduces a two-level data versioning mechanism to resolve conflicts in a speculative fashion even in the case of overflow. Our third and last contribution presents a couple of truly flexible HTM systems that can dynamically adapt their underlying mechanisms according to the characteristics of the program. DYNTM records statistics of previously executed transactions to select the best-suited strategy each time a new instance of a transaction starts. SWAPTM takes a different approach: it tracks information of the current transactional instance to change its priority level at runtime. Both alternatives obtain great performance over existing proposals that employ fixed transactional policies, especially in applications with phase changes. |
| publishDate |
2011 |
| dc.date.none.fl_str_mv |
2011 2012 2012 |
| dc.type.none.fl_str_mv |
info:eu-repo/semantics/doctoralThesis info:eu-repo/semantics/publishedVersion |
| format |
doctoralThesis |
| status_str |
publishedVersion |
| dc.identifier.none.fl_str_mv |
http://hdl.handle.net/10803/80383 https://dx.doi.org/10.5821/dissertation-2117-94562 |
| url |
http://hdl.handle.net/10803/80383 https://dx.doi.org/10.5821/dissertation-2117-94562 |
| dc.language.none.fl_str_mv |
Inglés |
| language_invalid_str_mv |
Inglés |
| dc.rights.none.fl_str_mv |
info:eu-repo/semantics/openAccess |
| eu_rights_str_mv |
openAccess |
| dc.format.none.fl_str_mv |
208 p. application/pdf application/pdf |
| dc.publisher.none.fl_str_mv |
Universitat Politècnica de Catalunya |
| publisher.none.fl_str_mv |
Universitat Politècnica de Catalunya |
| dc.source.none.fl_str_mv |
TDX (Tesis Doctorals en Xarxa) reponame:TDR. Tesis Doctorales en Red instname:CBUC, CESCA |
| instname_str |
CBUC, CESCA |
| reponame_str |
TDR. Tesis Doctorales en Red |
| collection |
TDR. Tesis Doctorales en Red |
| repository.name.fl_str_mv |
|
| repository.mail.fl_str_mv |
|
| _version_ |
1869410815172411392 |
| spelling |
Architectural support for high-performing hardware transactional memory systemsLupon Navazo, MarcHardware transactional memoryParallel programmingDynamically adaptive systemsNon-blocring synchronizationFASTMDYNTMSWPTM208004Parallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes the development of parallel software a hard and errorprone task. In addition to this, current synchronization techniques serialize the execution of those critical sections that conflict in shared memory and thus limit the scalability of multithreaded applications. Transactional Memory (TM) has emerged as a promising programming model that solves the trade-off between high performance and ease of use. In TM, the system is in charge of scheduling transactions (atomic blocks of instructions) and guaranteeing that they are executed in isolation, which simplifies writing parallel code and, at the same time, enables high concurrency when atomic regions access different data. Among all forms of TM environments, Hardware TM (HTM) systems is the only one that offers fast execution at the cost of adding dedicated logic in the processor. Existing HTMsystems suffer considerable delays when they execute complex transactional workloads, especially when they deal with large and contending transactions because they lack adaptability. Furthermore, most HTM implementations are ad hoc and require cumbersome hardware structures to be effective, which complicates the feasibility of the design. This thesis makes several contributions in the design and analysis of low-cost HTMsystems that yield good performance for any kind of TM program. Our first contribution, FASTM, introduces a novel mechanism to elegantly manage speculative (and already validated) versions of transactional data by slightly modifying on-chip memory engine. This approach permits fast recovery when a transaction that fits in private caches is discarded. At the same time, it keeps non-speculative values in software, which allows in-place x memory updates. Thus, FASTM is not hurt from capacity issues nor slows down when it has to undo transactional modifications. Our second contribution includes two different HTM systems that integrate deferred resolution of conflicts in a conventional multicore processor, which reduces the complexity of the system with respect to previous proposals. The first one, FUSETM, combines different-mode transactions under a unified infrastructure to gracefully handle resource overflow. As a result, FUSETM brings fast transactional computation without requiring additional hardware nor extra communication at the end of speculative execution. The second one, SPECTM, introduces a two-level data versioning mechanism to resolve conflicts in a speculative fashion even in the case of overflow. Our third and last contribution presents a couple of truly flexible HTM systems that can dynamically adapt their underlying mechanisms according to the characteristics of the program. DYNTM records statistics of previously executed transactions to select the best-suited strategy each time a new instance of a transaction starts. SWAPTM takes a different approach: it tracks information of the current transactional instance to change its priority level at runtime. Both alternatives obtain great performance over existing proposals that employ fixed transactional policies, especially in applications with phase changes.DOCTORAT EN ARQUITECTURA DE COMPUTADORS (Pla 2007)Universitat Politècnica de CatalunyaMagklis, GrigoriosGonzález Colás, AntonioUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors201220122011info:eu-repo/semantics/doctoralThesisinfo:eu-repo/semantics/publishedVersion208 p.application/pdfapplication/pdfhttp://hdl.handle.net/10803/80383https://dx.doi.org/10.5821/dissertation-2117-94562TDX (Tesis Doctorals en Xarxa)reponame:TDR. Tesis Doctorales en Redinstname:CBUC, CESCAInglésADVERTIMENT. L'accés als continguts d'aquesta tesi doctoral i la seva utilització ha de respectar els drets de la persona autora. Pot ser utilitzada per a consulta o estudi personal, així com en activitats o materials d'investigació i docència en els termes establerts a l'art. 32 del Text Refós de la Llei de Propietat Intel·lectual (RDL 1/1996). Per altres utilitzacions es requereix l'autorització prèvia i expressa de la persona autora. En qualsevol cas, en la utilització dels seus continguts caldrà indicar de forma clara el nom i cognoms de la persona autora i el títol de la tesi doctoral. No s'autoritza la seva reproducció o altres formes d'explotació efectuades amb finalitats de lucre ni la seva comunicació pública des d'un lloc aliè al servei TDX. Tampoc s'autoritza la presentació del seu contingut en una finestra o marc aliè a TDX (framing). Aquesta reserva de drets afecta tant als continguts de la tesi com als seus resums i índexs.info:eu-repo/semantics/openAccessoai:www.tdx.cat:10803/803832026-06-14T12:46:07Z |
| score |
15,300719 |