Speculative Vectorization for Superscalar Processors

Traditional vector architectures have been shown to be very effective in executing regular codes in which the compiler can detect data-level parallelism, i.e. repeating the same computation over different elements in the same code-level data structure.<br/><br/>A skilled programmer can e...

Descripción completa

Detalles Bibliográficos
Autor: Pajuelo González, Manuel Alejandro|||0000-0002-5510-6860
Tipo de recurso: tesis doctoral
Fecha de publicación:2005
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/93308
Acceso en línea:https://hdl.handle.net/2117/93308
https://dx.doi.org/10.5821/dissertation-2117-93308
Access Level:acceso abierto
Palabra clave:multimedia extensions
cost-effective vectorization
control independence
prefetch
Vectorizacion especulativa
speculative vectorization
Processament en paral·lel (Ordinadors)
Microprocessadors -- Disseny i construcció
Àrees temàtiques de la UPC::Informàtica
id ES_6f5f58bb4dd6bacad0d5e9c8e00fa9c8
oai_identifier_str oai:upcommons.upc.edu:2117/93308
network_acronym_str ES
network_name_str España
repository_id_str
dc.title.none.fl_str_mv Speculative Vectorization for Superscalar Processors
title Speculative Vectorization for Superscalar Processors
spellingShingle Speculative Vectorization for Superscalar Processors
Pajuelo González, Manuel Alejandro|||0000-0002-5510-6860
multimedia extensions
cost-effective vectorization
control independence
prefetch
Vectorizacion especulativa
speculative vectorization
Processament en paral·lel (Ordinadors)
Microprocessadors -- Disseny i construcció
Àrees temàtiques de la UPC::Informàtica
title_short Speculative Vectorization for Superscalar Processors
title_full Speculative Vectorization for Superscalar Processors
title_fullStr Speculative Vectorization for Superscalar Processors
title_full_unstemmed Speculative Vectorization for Superscalar Processors
title_sort Speculative Vectorization for Superscalar Processors
dc.creator.none.fl_str_mv Pajuelo González, Manuel Alejandro|||0000-0002-5510-6860
author Pajuelo González, Manuel Alejandro|||0000-0002-5510-6860
author_facet Pajuelo González, Manuel Alejandro|||0000-0002-5510-6860
author_role author
dc.contributor.none.fl_str_mv González Colás, Antonio María
dc.subject.none.fl_str_mv multimedia extensions
cost-effective vectorization
control independence
prefetch
Vectorizacion especulativa
speculative vectorization
Processament en paral·lel (Ordinadors)
Microprocessadors -- Disseny i construcció
Àrees temàtiques de la UPC::Informàtica
topic multimedia extensions
cost-effective vectorization
control independence
prefetch
Vectorizacion especulativa
speculative vectorization
Processament en paral·lel (Ordinadors)
Microprocessadors -- Disseny i construcció
Àrees temàtiques de la UPC::Informàtica
description Traditional vector architectures have been shown to be very effective in executing regular codes in which the compiler can detect data-level parallelism, i.e. repeating the same computation over different elements in the same code-level data structure.<br/><br/>A skilled programmer can easily create efficient vector code from regular applications. Unfortunately, this vectorization can be difficult if applications are not regular or if the programmer does not have an exact knowledge of the underlying architecture. <br/><br/>The compiler has a partial knowledge of the program (i.e. it has a limited knowledge of the values of the variables). Because of this, it generates code that is safe for any possible scenario according to its knowledge, and thus, it may lose significant opportunities to exploit SIMD parallelism. In addition to this, we have the problem of legacy codes that have been compiled for former versions of the ISA with no SIMD extensions, which are therefore not able to exploit new SIMD extensions incorporated into newer ISA versions.<br/><br/>In this dissertation, we will describe a mechanism that is able to detect and exploit DLP at runtime by speculatively creating vector instructions for prefetching and precomputing data for future instances of their scalar counterparts. This process will be called Speculative Dynamic Vectorization.<br/><br/>A more in-depth study of this technique reveals a very positive characteristic: the mechanism can easily be tailored to alleviate the main drawbacks of current superscalar processors, particularly branch mispredictions and the memory gap. In this dissertation, we will describe how to rearrange the basic Speculative Dynamic Vectorization mechanism to alleviate the branch misprediction penalty based on reusing control-flow independent instructions. The memory gap problem will be addressed with a set of mechanisms that exploit the stall cycles due to L2 misses in order to virtually enlarge the instruction window.<br/><br/>Finally, more refinements of the basic Speculative Dynamic Vectorization mechanism will be presented to improve its performance at a reasonable cost.
publishDate 2005
dc.date.none.fl_str_mv 2005
2005-11-24
2011
2011-04-12
dc.type.none.fl_str_mv doctoral thesis
http://purl.org/coar/resource_type/c_db06
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/doctoralThesis
format doctoralThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/93308
https://dx.doi.org/10.5821/dissertation-2117-93308
url https://hdl.handle.net/2117/93308
https://dx.doi.org/10.5821/dissertation-2117-93308
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universitat Politècnica de Catalunya
publisher.none.fl_str_mv Universitat Politècnica de Catalunya
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869410491204370432
spelling Speculative Vectorization for Superscalar ProcessorsPajuelo González, Manuel Alejandro|||0000-0002-5510-6860multimedia extensionscost-effective vectorizationcontrol independenceprefetchVectorizacion especulativaspeculative vectorizationProcessament en paral·lel (Ordinadors)Microprocessadors -- Disseny i construccióÀrees temàtiques de la UPC::InformàticaTraditional vector architectures have been shown to be very effective in executing regular codes in which the compiler can detect data-level parallelism, i.e. repeating the same computation over different elements in the same code-level data structure.<br/><br/>A skilled programmer can easily create efficient vector code from regular applications. Unfortunately, this vectorization can be difficult if applications are not regular or if the programmer does not have an exact knowledge of the underlying architecture. <br/><br/>The compiler has a partial knowledge of the program (i.e. it has a limited knowledge of the values of the variables). Because of this, it generates code that is safe for any possible scenario according to its knowledge, and thus, it may lose significant opportunities to exploit SIMD parallelism. In addition to this, we have the problem of legacy codes that have been compiled for former versions of the ISA with no SIMD extensions, which are therefore not able to exploit new SIMD extensions incorporated into newer ISA versions.<br/><br/>In this dissertation, we will describe a mechanism that is able to detect and exploit DLP at runtime by speculatively creating vector instructions for prefetching and precomputing data for future instances of their scalar counterparts. This process will be called Speculative Dynamic Vectorization.<br/><br/>A more in-depth study of this technique reveals a very positive characteristic: the mechanism can easily be tailored to alleviate the main drawbacks of current superscalar processors, particularly branch mispredictions and the memory gap. In this dissertation, we will describe how to rearrange the basic Speculative Dynamic Vectorization mechanism to alleviate the branch misprediction penalty based on reusing control-flow independent instructions. The memory gap problem will be addressed with a set of mechanisms that exploit the stall cycles due to L2 misses in order to virtually enlarge the instruction window.<br/><br/>Finally, more refinements of the basic Speculative Dynamic Vectorization mechanism will be presented to improve its performance at a reasonable cost.Los procesadores vectoriales han demostrado ser muy eficientes ejecutando códigos regulares en los que el compilador ha detectado Paralelismo a Nivel de Datos. Este paralelismo consiste en repetir los mismos cálculos en diferentes elementos de la misma estructura de alto nivel.<br/><br/>Un programador avanzado puede crear código vectorial eficiente para aplicaciones regulares. Por desgracia, esta vectorización puede llegar a ser compleja en aplicaciones regulares o si el programador no tiene suficiente conocimiento de la arquitectura sobre la que se va a ejecutar la aplicación.<br/><br/>El compilador tiene un conocimiento parcial del programa. Debido a esto, genera código que se puede ejecutar sin problemas en cualquier escenario según su conocimiento y, por tanto, puede perder oportunidades de explotar el paralelismo SIMD (Single Instruction Multiple Data). Además, existe el problema de los códigos de legado que han sido compilados con versiones anteriores del juego de instrucciones que no disponían de instrucciones SIMD lo cual hace que no se pueda explotar las extensiones SIMD de las nuevas versiones de los juegos de instrucciones.<br/><br/>En esta tesis se presentará un mecanismo capaz de detectar y explotar, en tiempo de ejecución, el paralelismo a nivel de datos mediante la creación especulativa de instrucciones vectoriales que prebusquen y precomputen valores para futuras instancias de instrucciones escalares. Este proceso se llamará Vectorización Dinámica Especulativa.<br/><br/>Un estudio más profundo de esta técnica conducirá a una conclusión muy importante: este mecanismo puede ser fácilmente modificado para aliviar algunos de los problemas más importantes de los procesadores superescalares. Estos problemas son: los fallos de predicción de saltos y el gap entre procesador y memoria. En esta tesis describiremos como modificar el mecanismo básico de Vectorización Dinámica Especulativa para reducir la penalización de rendimiento producida por los fallos de predicción de saltos mediante el reuso de datos de instrucciones independientes de control. <br/><br/>Además, se presentará un conjunto de técnicas que explotan los ciclos de bloqueo del procesador debidos a un fallo en la cache de segundo nivel mediante un agrandamiento virtual de la ventana de instrucciones. Esto reducirá la penalización del problema del gap entre procesador y memoria.<br/><br/>Finalmente, se presentarán refinamientos del mecanismo básico de Vectorización Dinámica Especulativa enfocados a mejorar el rendimiento de éste a un bajo coste.Universitat Politècnica de CatalunyaGonzález Colás, Antonio María20052005-11-2420112011-04-12doctoral thesishttp://purl.org/coar/resource_type/c_db06VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/doctoralThesisapplication/pdfhttps://hdl.handle.net/2117/93308https://dx.doi.org/10.5821/dissertation-2117-93308reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/933082026-05-27T15:37:01Z
score 15.301603

Similares en LA Referencia