Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this p...

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Detalles Bibliográficos
Autores: Champac Vilela, Víctor Hugo, Avendaño, Victor, Figueras Pàmies, Joan
Tipo de recurso: artículo
Fecha de publicación:2010
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/7805
Acceso en línea:https://hdl.handle.net/2117/7805
https://dx.doi.org/10.1109/TVLSI.2008.2010398
Access Level:acceso abierto
Palabra clave:Digital integrated circuits
Integrated circuits--Design
Integrated circuits--Testing
Circuits integrats digitals
Circuits integrats digitals -- Disseny
Circuits integrats digitals -- Proves
Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
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spelling Built-In Sensor for Signal Integrity Faults in Digital Interconnect SignalsChampac Vilela, Víctor HugoAvendaño, VictorFigueras Pàmies, JoanDigital integrated circuitsIntegrated circuits--DesignIntegrated circuits--TestingCircuits integrats digitalsCircuits integrats digitals -- DissenyCircuits integrats digitals -- ProvesÀrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònicsTesting of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.20102010-02-0120102010-06-22journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/2117/7805https://dx.doi.org/10.1109/TVLSI.2008.2010398reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/78052026-05-27T15:37:01Z
dc.title.none.fl_str_mv Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals
title Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals
spellingShingle Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals
Champac Vilela, Víctor Hugo
Digital integrated circuits
Integrated circuits--Design
Integrated circuits--Testing
Circuits integrats digitals
Circuits integrats digitals -- Disseny
Circuits integrats digitals -- Proves
Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
title_short Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals
title_full Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals
title_fullStr Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals
title_full_unstemmed Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals
title_sort Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals
dc.creator.none.fl_str_mv Champac Vilela, Víctor Hugo
Avendaño, Victor
Figueras Pàmies, Joan
author Champac Vilela, Víctor Hugo
author_facet Champac Vilela, Víctor Hugo
Avendaño, Victor
Figueras Pàmies, Joan
author_role author
author2 Avendaño, Victor
Figueras Pàmies, Joan
author2_role author
author
dc.subject.none.fl_str_mv Digital integrated circuits
Integrated circuits--Design
Integrated circuits--Testing
Circuits integrats digitals
Circuits integrats digitals -- Disseny
Circuits integrats digitals -- Proves
Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
topic Digital integrated circuits
Integrated circuits--Design
Integrated circuits--Testing
Circuits integrats digitals
Circuits integrats digitals -- Disseny
Circuits integrats digitals -- Proves
Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
description Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.
publishDate 2010
dc.date.none.fl_str_mv 2010
2010-02-01
2010
2010-06-22
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/7805
https://dx.doi.org/10.1109/TVLSI.2008.2010398
url https://hdl.handle.net/2117/7805
https://dx.doi.org/10.1109/TVLSI.2008.2010398
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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