A modified ART 1 algorithm more suitable for VLSI implementations

El pdf del artículo es la versión post-print.

Detalles Bibliográficos
Autores: Serrano-Gotarredona, Teresa, Linares-Barranco, Bernabé
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:1996
País:España
Institución:Consejo Superior de Investigaciones Científicas (CSIC)
Repositorio:DIGITAL.CSIC. Repositorio Institucional del CSIC
OAI Identifier:oai:digital.csic.es:10261/84833
Acceso en línea:http://hdl.handle.net/10261/84833
Access Level:acceso abierto
Palabra clave:ART
VLSI-friendly algorithms
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spelling A modified ART 1 algorithm more suitable for VLSI implementationsSerrano-Gotarredona, TeresaLinares-Barranco, BernabéARTVLSI-friendly algorithmsEl pdf del artículo es la versión post-print.This paper presents a modification to the original ART 1 algorithm (Carpenter and Grossberg, 1987a, A massively parallel architecture for a self-organizing neural pattern recognition machine, Computer Vision, Graphics, and Image Processing, 37, 54–115) that is conceptually similar, can be implemented in hardware with less sophisticated building blocks, and maintains the computational capabilities of the originally proposed algorithm. This modified ART 1 algorithm (which we will call here ART 1m) is the result of hardware motivated simplifications investigated during the design of an actual ART 1 chip [Serrano-Gotarredona et al., 1994, Proc. 1994 IEEE Int. Conf. Neural Networks (Vol. 3, pp. 1912–1916); Serrano-Gotarredona and Linares-Barranco, 1996, IEEE Trans. VLSI Systems, (in press)]. The purpose of this paper is simply to justify theoretically that the modified algorithm preserves the computational properties of the original one and to study the difference in behavior between the two approaches.Peer reviewedElsevier201320131996info:eu-repo/semantics/articlehttp://purl.org/coar/resource_type/c_6501Postprintinfo:eu-repo/semantics/acceptedVersionhttp://hdl.handle.net/10261/84833reponame:DIGITAL.CSIC. Repositorio Institucional del CSICinstname:Consejo Superior de Investigaciones Científicas (CSIC)Ingléshttp://www.sciencedirect.com/science/article/pii/089360809500145X#info:eu-repo/semantics/openAccessoai:digital.csic.es:10261/848332026-05-22T06:33:51Z
dc.title.none.fl_str_mv A modified ART 1 algorithm more suitable for VLSI implementations
title A modified ART 1 algorithm more suitable for VLSI implementations
spellingShingle A modified ART 1 algorithm more suitable for VLSI implementations
Serrano-Gotarredona, Teresa
ART
VLSI-friendly algorithms
title_short A modified ART 1 algorithm more suitable for VLSI implementations
title_full A modified ART 1 algorithm more suitable for VLSI implementations
title_fullStr A modified ART 1 algorithm more suitable for VLSI implementations
title_full_unstemmed A modified ART 1 algorithm more suitable for VLSI implementations
title_sort A modified ART 1 algorithm more suitable for VLSI implementations
dc.creator.none.fl_str_mv Serrano-Gotarredona, Teresa
Linares-Barranco, Bernabé
author Serrano-Gotarredona, Teresa
author_facet Serrano-Gotarredona, Teresa
Linares-Barranco, Bernabé
author_role author
author2 Linares-Barranco, Bernabé
author2_role author
dc.subject.none.fl_str_mv ART
VLSI-friendly algorithms
topic ART
VLSI-friendly algorithms
description El pdf del artículo es la versión post-print.
publishDate 1996
dc.date.none.fl_str_mv 1996
2013
2013
dc.type.none.fl_str_mv info:eu-repo/semantics/article
http://purl.org/coar/resource_type/c_6501
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dc.identifier.none.fl_str_mv http://hdl.handle.net/10261/84833
url http://hdl.handle.net/10261/84833
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
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eu_rights_str_mv openAccess
dc.publisher.none.fl_str_mv Elsevier
publisher.none.fl_str_mv Elsevier
dc.source.none.fl_str_mv reponame:DIGITAL.CSIC. Repositorio Institucional del CSIC
instname:Consejo Superior de Investigaciones Científicas (CSIC)
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