A high-voltage floating level shifter for a multi-stage charge-pump in a standard 1.8 V/3.3 V CMOS process
This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from 3 V to 8.5 V with a delay response of 1.8 ns and occupies 0.008 mm2. The prop...
| Authors: | , , |
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| Format: | article |
| Status: | Published version |
| Publication Date: | 2022 |
| Country: | España |
| Institution: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repository: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/336821 |
| Online Access: | http://hdl.handle.net/10261/336821 |
| Access Level: | Open access |
| Keyword: | Level shifter Gate driver CMOS Charge pump High-voltage compliance |
| Summary: | This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from 3 V to 8.5 V with a delay response of 1.8 ns and occupies 0.008 mm2. The proposed circuit has been used in a multi-stage charge pump for programming its voltage conversion ratio. Experimental results show that the level shifters successfully enable/disable the stages of the charge pump, thus modifying its output voltage between 5.35 V and 12.4 V for an output current of 3 mA. |
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