Develop SPI slave Interface IP for reuse in ASIC designs
This thesis presents the design of a reusable SPI Slave IP core for ASIC integration. The IP supports full-duplex communication, 8- and 16-bit data, and daisy chain connections for up to 63 devices. It is designed with modularity, low power consumption through clock gating, and signal integrity in m...
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| Formato: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/450606 |
| Acesso em linha: | https://hdl.handle.net/2117/450606 |
| Access Level: | acceso abierto |
| Palavra-chave: | Integrated circuits--Design and construction Digital design SPI Clock Domian Crossing Synthesis Circuits integrats--Disseny i construcció Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| Resumo: | This thesis presents the design of a reusable SPI Slave IP core for ASIC integration. The IP supports full-duplex communication, 8- and 16-bit data, and daisy chain connections for up to 63 devices. It is designed with modularity, low power consumption through clock gating, and signal integrity in mind. Functional verification is performed using UVM, and DFT logic is integrated for testability. The final implementation meets ASIC requirements in terms of area, timing, and power, offering a flexible and efficient SPI solution for digital control applications. |
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