Multi-node Address Event Ring Communication System for Spiking Neural Network implementation
This thesis has focused on introducing a multi node functionality on a spiking neural processor (HEENSMB) while maintaining the newly added features of the HEENS OneBoard system as well as keeping the array size as large as possible. In order to introduce the multi node functionality, the system has...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2023 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/404445 |
| Acceso en línea: | https://hdl.handle.net/2117/404445 |
| Access Level: | acceso abierto |
| Palabra clave: | Neural networks (Computer science) HEENS Neural Network AER-SRT Xarxes neuronals (Informàtica) Àrees temàtiques de la UPC::Informàtica::Intel·ligència artificial |
| Sumario: | This thesis has focused on introducing a multi node functionality on a spiking neural processor (HEENSMB) while maintaining the newly added features of the HEENS OneBoard system as well as keeping the array size as large as possible. In order to introduce the multi node functionality, the system has been enhanced to be able to reset all nodes and ensure a synchronous start, aiding in the scalability of the HEENS architecture and introducing a simple way of resynchronizing the entire system. In order to facilitate scalability within the HEENS architecture, the ID?s used and ring size are made configurable. The configuration of the program instructions and synapses can be loaded onto the system through the master node, which will then distribute it to all slave nodes, allowing easy reconfiguration within seconds. Synchronization during the emulation cycle is controlled by the master node and followed by all slave nodes. Through a second finish packet at the end of the distribution phase, it is ensured that all slaves stay in sync. Next to this, it is now possible to monitor up to four neuron potentials of any four neurons within the entire ring, while having a 9x16 array size (times 8 total layers) for a total of 1152 neurons per node. It is not required for any node to have the same array size as the master. The new HEENS-MB architecture described in VHDL has been implemented and verified using simulations in Questasim Advanced Simulator tool using three nodes and has been tested with two AMD Zync 7000 SoC ZC706 Evaluation boards. The evaluation boards have been connected with each other in a loop using the high-speed GTX interface and tested using four different neural networks. The networks used the LIF neural model, able to use global synapses (board-to-board connections). Overall, the Multi-node address event ring communication system implemented in the HEENS-MB architecture is fully functional now and can be expanded to also support Kintex family FPGA devices in order to create larger neural networks. In addition, further work can be done in the expansion of the HDMI display in order to display more than 1000 neurons and the system could be expanded with the logging capability for neuron potentials. |
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