Design and implementation of an Envelope tracking Power Amplifier using switched Amplifiers and slow Envelopes
English: This master thesis presents the design and implementation of an Envelope Tracking (ET) transmitter including an envelope amplifier based on switched power amplifiers and algorithms for slew-rate and bandwidth reduction. The ET transmitter here presented constitutes a research environment th...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2011 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2099.1/12746 |
| Acceso en línea: | https://hdl.handle.net/2099.1/12746 |
| Access Level: | acceso abierto |
| Palabra clave: | Audio amplifiers Power amplifier Envelope tracking Envelope amplifier Slow envelope. Slow envelope Amplificadors (Electrònica) Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència |
| Sumario: | English: This master thesis presents the design and implementation of an Envelope Tracking (ET) transmitter including an envelope amplifier based on switched power amplifiers and algorithms for slew-rate and bandwidth reduction. The ET transmitter here presented constitutes a research environment that will allow investigate possible solutions to solve the linearity-efficiency trade-off of the power amplifiers. The design and implementation of the envelope amplifier includes commercial switching devices driven by pulsed signals generated by a Field Programmable Gate Array (FPGA). The pulsed signals are modulated using Pulse Width Modulation and Delta-Sigma Modulation aimed to achieve a high efficient amplification. The signals, amplitudes, modulation frequencies and bandwidths used during the design and implementation are compatible with current communications standards. This master thesis also presents a new algorithm for reduction of the envelope bandwidth as well as improvements over the existing slew-rate reduction algorithm presented in a previous publication. These improvements were implemented in the FPGA and validated in the implemented transmitter. Results show that switching amplification is limited by the availability of current technologies in this field and the algorithms for reducing slew rate and bandwidth of the envelope are suitable to overcome this limitation while new technologies allow higher switching frequencies. |
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