Mapping arbitrary logic functions onto carry chains in FPGAs

Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike ot...

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Detalhes bibliográficos
Autores: Senhadji Navarro, Raouf, García Vargas, Ignacio
Formato: artículo
Estado:Versión publicada
Fecha de publicación:2022
País:España
Recursos:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/134956
Acesso em linha:https://hdl.handle.net/11441/134956
https://doi.org/10.3390/electronics11010027
Access Level:acceso abierto
Palavra-chave:Carry chain
Logic synthesis
Field Programmable Gate Array (FPGA)
Technology mapping
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spelling Mapping arbitrary logic functions onto carry chains in FPGAsSenhadji Navarro, RaoufGarcía Vargas, IgnacioCarry chainLogic synthesisField Programmable Gate Array (FPGA)Technology mappingCurrent Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be applied to any logic function. The presented technique includes: (1) an architecture that is composed of blocks that implement AND and OR functions (called CANDs and CORs, respectively) by means of Look-Up-Tables (LUTs) and carry-chain resources; and (2) a mapping algorithm to reduce both the delay of the critical path and the number of used FPGA resources. The algorithm uses a heuristic to interconnect CORs and CANDs in order to reduce the delay. The problem of mapping the maxterms (or minterms) of a function to LUTs has been modelled as a Set Bin Packing (SBP) problem. Since SBP is NP-Hard, a greedy algorithm has been proposed, which is based on the First Fit Decreasing (FFD) heuristic. The results obtained have been compared with the conventional technique using both speed and area optimization. For this purpose, a large synthetic set of test cases has been generated. The proposed technique improves both the speed and area results for the vast majority of functions whose conventional implementation requires more than four logic levels. It is important to highlight that the improvement of one parameter (speed or area) is not achieved at the expense of the other.MDPIArquitectura y Tecnología de Computadores2022info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/134956https://doi.org/10.3390/electronics11010027reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésElectronics, 11 (1 - art. nº27)https://www.mdpi.com/2079-9292/11/1/27info:eu-repo/semantics/openAccessoai:idus.us.es:11441/1349562026-06-17T12:51:07Z
dc.title.none.fl_str_mv Mapping arbitrary logic functions onto carry chains in FPGAs
title Mapping arbitrary logic functions onto carry chains in FPGAs
spellingShingle Mapping arbitrary logic functions onto carry chains in FPGAs
Senhadji Navarro, Raouf
Carry chain
Logic synthesis
Field Programmable Gate Array (FPGA)
Technology mapping
title_short Mapping arbitrary logic functions onto carry chains in FPGAs
title_full Mapping arbitrary logic functions onto carry chains in FPGAs
title_fullStr Mapping arbitrary logic functions onto carry chains in FPGAs
title_full_unstemmed Mapping arbitrary logic functions onto carry chains in FPGAs
title_sort Mapping arbitrary logic functions onto carry chains in FPGAs
dc.creator.none.fl_str_mv Senhadji Navarro, Raouf
García Vargas, Ignacio
author Senhadji Navarro, Raouf
author_facet Senhadji Navarro, Raouf
García Vargas, Ignacio
author_role author
author2 García Vargas, Ignacio
author2_role author
dc.contributor.none.fl_str_mv Arquitectura y Tecnología de Computadores
dc.subject.none.fl_str_mv Carry chain
Logic synthesis
Field Programmable Gate Array (FPGA)
Technology mapping
topic Carry chain
Logic synthesis
Field Programmable Gate Array (FPGA)
Technology mapping
description Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be applied to any logic function. The presented technique includes: (1) an architecture that is composed of blocks that implement AND and OR functions (called CANDs and CORs, respectively) by means of Look-Up-Tables (LUTs) and carry-chain resources; and (2) a mapping algorithm to reduce both the delay of the critical path and the number of used FPGA resources. The algorithm uses a heuristic to interconnect CORs and CANDs in order to reduce the delay. The problem of mapping the maxterms (or minterms) of a function to LUTs has been modelled as a Set Bin Packing (SBP) problem. Since SBP is NP-Hard, a greedy algorithm has been proposed, which is based on the First Fit Decreasing (FFD) heuristic. The results obtained have been compared with the conventional technique using both speed and area optimization. For this purpose, a large synthetic set of test cases has been generated. The proposed technique improves both the speed and area results for the vast majority of functions whose conventional implementation requires more than four logic levels. It is important to highlight that the improvement of one parameter (speed or area) is not achieved at the expense of the other.
publishDate 2022
dc.date.none.fl_str_mv 2022
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/134956
https://doi.org/10.3390/electronics11010027
url https://hdl.handle.net/11441/134956
https://doi.org/10.3390/electronics11010027
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv Electronics, 11 (1 - art. nº27)
https://www.mdpi.com/2079-9292/11/1/27
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv MDPI
publisher.none.fl_str_mv MDPI
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,301603

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