Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems

In Hard Real-time Systems, the execution of tasks must be completed within a certain timeframe, known as deadline. In consequence, when a hard-real time system is designed, it is strictly necessary to assume that its tasks will always take their Worst Case Execution Time (WCET), to make sure they me...

ver descrição completa

Detalhes bibliográficos
Autor: Rufart Blasco, Eric
Tipo de documento: dissertação
Data de publicação:2023
País:España
Recursos:Universitat Politècnica de Catalunya (UPC)
Repositório:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglês
OAI Identifier:oai:upcommons.upc.edu:2117/404796
Acesso em linha:https://hdl.handle.net/2117/404796
Access Level:Acceso aberto
Palavra-chave:Real-time data processing
RISC microprocessors
Timing
Probabilistic logic
Hardware
Layout
processor cache design
real-time critical systems
WCET
MBPTA
MBPTA compliant
measurement-based probabilistic timing analysis
Probabilistic WCET (pWCET)
EVT-based timing analysis
hardware architectures
pWCET computation
MBPTA-CV
Extreme Value Theory(EVT)
Temps real (Informàtica)
RISC (Microprocessadors)
Àrees temàtiques de la UPC::Informàtica::Enginyeria del software
id ES_4c7bc6aa3126c460c7bbabd3092fb2e0
oai_identifier_str oai:upcommons.upc.edu:2117/404796
network_acronym_str ES
network_name_str España
repository_id_str
spelling Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time SystemsRufart Blasco, EricReal-time data processingRISC microprocessorsTimingProbabilistic logicHardwareLayoutprocessor cache designreal-time critical systemsWCETMBPTAMBPTA compliantmeasurement-based probabilistic timing analysisProbabilistic WCET (pWCET)EVT-based timing analysishardware architecturespWCET computationMBPTA-CVExtreme Value Theory(EVT)Temps real (Informàtica)RISC (Microprocessadors)Àrees temàtiques de la UPC::Informàtica::Enginyeria del softwareIn Hard Real-time Systems, the execution of tasks must be completed within a certain timeframe, known as deadline. In consequence, when a hard-real time system is designed, it is strictly necessary to assume that its tasks will always take their Worst Case Execution Time (WCET), to make sure they meet their deadlines. For this reason, Worst Case Execution Times defines the maximum performance of processors in these systems. Since the performance requirements of modern Hard Real-time Systems are rapidly increasing, the use of newer and higher performance processors is needed. However, these processors have a much greater internal complexity compared to the ones previously used in these systems. This complexity can be detrimental given that Worst Case Execution Times, which are critical for these systems, are often estimated using traditional timing analysis methods like Static and Measurement-based deterministic techniques. The need for extremely detailed knowledge of the processor's internals, IP restrictions, and the impossibility of modeling certain features leads to extremely pessimistic assumptions and the disabling of features while using these techniques. On the other hand, Measurement-Based Probabilistic Timing Analysis (MBPTA) allows computing probabilistic WCET estimates easily on top of more complex hardware. This can only be performed when Time Randomisation is introduced in the microarchitectural design, e.g. namely through time-randomised cache designs. Despite their better WCET compared to conventional caches, time-randomised caches provide lower average performance. In this work, we perform the following contributions. First, we add MBPTA support in a commercial RISC-V processor for real-time systems. We show how branch prediction can become MBPTA-compliant, and in conjunction with a cache-locking mechanism can increase the front-end performance of an MBPTA compliant processor. Our evaluation demonstrates benefits both in terms of average case as well as in worst case performance.Universitat Politècnica de CatalunyaKosmidis, Leonidas20232023-10-2020242024-03-18master thesishttp://purl.org/coar/resource_type/c_bdccNAhttp://purl.org/coar/version/c_be7fb7dd8ff6fe43info:eu-repo/semantics/masterThesisapplication/pdfhttps://hdl.handle.net/2117/404796reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/4047962026-05-27T15:37:01Z
dc.title.none.fl_str_mv Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems
title Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems
spellingShingle Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems
Rufart Blasco, Eric
Real-time data processing
RISC microprocessors
Timing
Probabilistic logic
Hardware
Layout
processor cache design
real-time critical systems
WCET
MBPTA
MBPTA compliant
measurement-based probabilistic timing analysis
Probabilistic WCET (pWCET)
EVT-based timing analysis
hardware architectures
pWCET computation
MBPTA-CV
Extreme Value Theory(EVT)
Temps real (Informàtica)
RISC (Microprocessadors)
Àrees temàtiques de la UPC::Informàtica::Enginyeria del software
title_short Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems
title_full Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems
title_fullStr Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems
title_full_unstemmed Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems
title_sort Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems
dc.creator.none.fl_str_mv Rufart Blasco, Eric
author Rufart Blasco, Eric
author_facet Rufart Blasco, Eric
author_role author
dc.contributor.none.fl_str_mv Kosmidis, Leonidas
dc.subject.none.fl_str_mv Real-time data processing
RISC microprocessors
Timing
Probabilistic logic
Hardware
Layout
processor cache design
real-time critical systems
WCET
MBPTA
MBPTA compliant
measurement-based probabilistic timing analysis
Probabilistic WCET (pWCET)
EVT-based timing analysis
hardware architectures
pWCET computation
MBPTA-CV
Extreme Value Theory(EVT)
Temps real (Informàtica)
RISC (Microprocessadors)
Àrees temàtiques de la UPC::Informàtica::Enginyeria del software
topic Real-time data processing
RISC microprocessors
Timing
Probabilistic logic
Hardware
Layout
processor cache design
real-time critical systems
WCET
MBPTA
MBPTA compliant
measurement-based probabilistic timing analysis
Probabilistic WCET (pWCET)
EVT-based timing analysis
hardware architectures
pWCET computation
MBPTA-CV
Extreme Value Theory(EVT)
Temps real (Informàtica)
RISC (Microprocessadors)
Àrees temàtiques de la UPC::Informàtica::Enginyeria del software
description In Hard Real-time Systems, the execution of tasks must be completed within a certain timeframe, known as deadline. In consequence, when a hard-real time system is designed, it is strictly necessary to assume that its tasks will always take their Worst Case Execution Time (WCET), to make sure they meet their deadlines. For this reason, Worst Case Execution Times defines the maximum performance of processors in these systems. Since the performance requirements of modern Hard Real-time Systems are rapidly increasing, the use of newer and higher performance processors is needed. However, these processors have a much greater internal complexity compared to the ones previously used in these systems. This complexity can be detrimental given that Worst Case Execution Times, which are critical for these systems, are often estimated using traditional timing analysis methods like Static and Measurement-based deterministic techniques. The need for extremely detailed knowledge of the processor's internals, IP restrictions, and the impossibility of modeling certain features leads to extremely pessimistic assumptions and the disabling of features while using these techniques. On the other hand, Measurement-Based Probabilistic Timing Analysis (MBPTA) allows computing probabilistic WCET estimates easily on top of more complex hardware. This can only be performed when Time Randomisation is introduced in the microarchitectural design, e.g. namely through time-randomised cache designs. Despite their better WCET compared to conventional caches, time-randomised caches provide lower average performance. In this work, we perform the following contributions. First, we add MBPTA support in a commercial RISC-V processor for real-time systems. We show how branch prediction can become MBPTA-compliant, and in conjunction with a cache-locking mechanism can increase the front-end performance of an MBPTA compliant processor. Our evaluation demonstrates benefits both in terms of average case as well as in worst case performance.
publishDate 2023
dc.date.none.fl_str_mv 2023
2023-10-20
2024
2024-03-18
dc.type.none.fl_str_mv master thesis
http://purl.org/coar/resource_type/c_bdcc
NA
http://purl.org/coar/version/c_be7fb7dd8ff6fe43
dc.type.openaire.fl_str_mv info:eu-repo/semantics/masterThesis
format masterThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/404796
url https://hdl.handle.net/2117/404796
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universitat Politècnica de Catalunya
publisher.none.fl_str_mv Universitat Politècnica de Catalunya
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869407630465695744
score 15,198674

Registros relacionados