A DRAM/SRAM memory scheme for fast packet buffers
We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2006 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/106017 |
| Acceso en línea: | https://hdl.handle.net/2117/106017 https://dx.doi.org/10.1109/TC.2006.63 |
| Access Level: | acceso abierto |
| Palabra clave: | Routing (Computer network management) Router architecture Packet buffers High-performance memory systems Storage schemes Encaminadors (Xarxes d'ordinadors) Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors |
| Sumario: | We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps. |
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