Real-time estimation of zero crossings of sampled signals for timing using cubic spline interpolation
[EN] A scheme is proposed for hardware estimation of the location of zero crossings of sampled signals with sub-sample resolution for timing applications, that consists in interpolating the signal with a cubic spline near the zero crossing and then finding the root of the resulting polynomial. An it...
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2017 |
| País: | España |
| Institución: | Universitat Politècnica de València (UPV) |
| Repositorio: | RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia |
| Idioma: | inglés |
| OAI Identifier: | oai:riunet.upv.es:10251/140833 |
| Acceso en línea: | https://riunet.upv.es/handle/10251/140833 |
| Access Level: | acceso abierto |
| Palabra clave: | Interpolation Splines (mathematics) Estimation Timing Hardware Registers Real-time systems TECNOLOGIA ELECTRONICA |
| Sumario: | [EN] A scheme is proposed for hardware estimation of the location of zero crossings of sampled signals with sub-sample resolution for timing applications, that consists in interpolating the signal with a cubic spline near the zero crossing and then finding the root of the resulting polynomial. An iterative algorithm based on the bisection method is presented that obtains one bit of the result per step and admits an efficient FPGA implementation using fixed-point representation. In particular, the root estimation iteration involves only two additions, and the initial values can be obtained from FIR filters with certain symmetry properties. It is shown that this allows online, real-time estimation of timestamps in free-running sampling detector systems with improved accuracy with respect to the more common linear interpolation. The method is evaluated with simulations using ideal and real timing signals and estimates are given for the resource usage and speed of its implementation. |
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