Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions
In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias Temperature Instability and Hot-Carrier Injection phenomena can lead to progres...
| Autores: | , , , , , , , |
|---|---|
| Tipo de recurso: | artículo |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2021 |
| País: | España |
| Institución: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/162388 |
| Acceso en línea: | https://hdl.handle.net/11441/162388 https://doi.org/10.1016/j.sse.2021.108037 |
| Access Level: | acceso abierto |
| Palabra clave: | CMOS BTI HCI Parameters Extraction Method RTN Defects Aging |
| Sumario: | In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias Temperature Instability and Hot-Carrier Injection phenomena can lead to progressive deviations of the circuit performance or even to its catastrophic failure. In this scenario, and to understand the effects of these variability sources, an extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models and simulation tools needed to achieve reliable integrated circuits. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at nominal and accelerated aging conditions. To this end, a versatile transistor array chip and a flexible measurement setup have been used to reduce the required testing time to attainable values. |
|---|