FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options

This is the author’s version of a work that was accepted for publication in Journal of Systems Architecture. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Ch...

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Autores: Sánchez Román, Diego, Moreno, Víctor, López Buedo, Sergio, Sutter Capristo, Gustavo Daniel, González Martínez, Iván, Gómez Arribas, Fco. Javier, Aracil Rico, Javier
Tipo de recurso: artículo
Fecha de publicación:2013
País:España
Institución:Universidad Autónoma de Madrid
Repositorio:Biblos-e Archivo. Repositorio Institucional de la UAM
Idioma:inglés
OAI Identifier:oai:repositorio.uam.es:10486/667235
Acceso en línea:http://hdl.handle.net/10486/667235
https://dx.doi.org/10.1016/j.sysarc.2013.01.004
Access Level:acceso abierto
Palabra clave:Field programmable gate arrays
Financial data processing
Floating-point arithmetic
High level language synthesis
Parallel machines
Informática
Telecomunicaciones
id ES_43b89398fc92a5f9b101cb987bfb9541
oai_identifier_str oai:repositorio.uam.es:10486/667235
network_acronym_str ES
network_name_str España
repository_id_str
spelling FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex optionsSánchez Román, DiegoMoreno, VíctorLópez Buedo, SergioSutter Capristo, Gustavo DanielGonzález Martínez, IvánGómez Arribas, Fco. JavierAracil Rico, JavierField programmable gate arraysFinancial data processingFloating-point arithmeticHigh level language synthesisParallel machinesInformáticaTelecomunicacionesThis is the author’s version of a work that was accepted for publication in Journal of Systems Architecture. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Journal of Systems Architecture, 59, 3 (2013) DOI: 10.1016/j.sysarc.2013.01.004In this paper we present an FPGA implementation of a Monte-Carlo method for pricing Asian options using Impulse C and floating-point arithmetic. In an Altera Stratix-V FPGA, a 149x speedup factor was obtained against an OpenMP-based solution in a 4-core Intel Core i7 processor. This speedup is comparable to that reported in the literature using a classic HDL-based methodology, but the development time is significantly reduced. Additionally, the use of a HLL-based methodology allowed us to implement a high-quality Gaussian random number generator, which produces more precise results than those obtained with the simple generators usually present in HDL-based designs.Elsevier BVDepartamento de Tecnología Electrónica y de las ComunicacionesEscuela Politécnica SuperiorComputación y Redes de Altas Prestaciones (ING EPS-004)20132013-03-01research articlehttp://purl.org/coar/resource_type/c_2df8fbb1AMhttp://purl.org/coar/version/c_ab4af688f83e57aainfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10486/667235https://dx.doi.org/10.1016/j.sysarc.2013.01.004reponame:Biblos-e Archivo. Repositorio Institucional de la UAMinstname:Universidad Autónoma de MadridInglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:repositorio.uam.es:10486/6672352026-06-23T12:46:27Z
dc.title.none.fl_str_mv FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options
title FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options
spellingShingle FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options
Sánchez Román, Diego
Field programmable gate arrays
Financial data processing
Floating-point arithmetic
High level language synthesis
Parallel machines
Informática
Telecomunicaciones
title_short FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options
title_full FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options
title_fullStr FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options
title_full_unstemmed FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options
title_sort FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options
dc.creator.none.fl_str_mv Sánchez Román, Diego
Moreno, Víctor
López Buedo, Sergio
Sutter Capristo, Gustavo Daniel
González Martínez, Iván
Gómez Arribas, Fco. Javier
Aracil Rico, Javier
author Sánchez Román, Diego
author_facet Sánchez Román, Diego
Moreno, Víctor
López Buedo, Sergio
Sutter Capristo, Gustavo Daniel
González Martínez, Iván
Gómez Arribas, Fco. Javier
Aracil Rico, Javier
author_role author
author2 Moreno, Víctor
López Buedo, Sergio
Sutter Capristo, Gustavo Daniel
González Martínez, Iván
Gómez Arribas, Fco. Javier
Aracil Rico, Javier
author2_role author
author
author
author
author
author
dc.contributor.none.fl_str_mv Departamento de Tecnología Electrónica y de las Comunicaciones
Escuela Politécnica Superior
Computación y Redes de Altas Prestaciones (ING EPS-004)
dc.subject.none.fl_str_mv Field programmable gate arrays
Financial data processing
Floating-point arithmetic
High level language synthesis
Parallel machines
Informática
Telecomunicaciones
topic Field programmable gate arrays
Financial data processing
Floating-point arithmetic
High level language synthesis
Parallel machines
Informática
Telecomunicaciones
description This is the author’s version of a work that was accepted for publication in Journal of Systems Architecture. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Journal of Systems Architecture, 59, 3 (2013) DOI: 10.1016/j.sysarc.2013.01.004
publishDate 2013
dc.date.none.fl_str_mv 2013
2013-03-01
dc.type.none.fl_str_mv research article
http://purl.org/coar/resource_type/c_2df8fbb1
AM
http://purl.org/coar/version/c_ab4af688f83e57aa
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv http://hdl.handle.net/10486/667235
https://dx.doi.org/10.1016/j.sysarc.2013.01.004
url http://hdl.handle.net/10486/667235
https://dx.doi.org/10.1016/j.sysarc.2013.01.004
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Elsevier BV
publisher.none.fl_str_mv Elsevier BV
dc.source.none.fl_str_mv reponame:Biblos-e Archivo. Repositorio Institucional de la UAM
instname:Universidad Autónoma de Madrid
instname_str Universidad Autónoma de Madrid
reponame_str Biblos-e Archivo. Repositorio Institucional de la UAM
collection Biblos-e Archivo. Repositorio Institucional de la UAM
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869407043596582912
score 15.300724

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