Combining static and dynamic data coalescing in unified parallel C
Significant progress has been made in the development of programming languages and tools that are suitable for hybrid computer architectures that group several shared-memory multicores interconnected through a network. This paper addresses important limitations in the code generation for partitioned...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2015 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/91115 |
| Acceso en línea: | https://hdl.handle.net/2117/91115 https://dx.doi.org/10.1109/TPDS.2015.2405551 |
| Access Level: | acceso abierto |
| Palabra clave: | Parallel processing (Electronic computers) C (Computer program language) One-sided communication Partitioned global address space Performance evaluation Unified parallel C Processament en paral·lel (Ordinadors) C (Llenguatge de programació) Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures distribuïdes |
| Sumario: | Significant progress has been made in the development of programming languages and tools that are suitable for hybrid computer architectures that group several shared-memory multicores interconnected through a network. This paper addresses important limitations in the code generation for partitioned global address space (PGAS) languages. These languages allow fine-grained communication and lead to programs that perform many fine-grained accesses to data. When the data is distributed to remote computing nodes, code transformations are required to prevent performance degradation. Until now code transformations to PGAS programs have been restricted to the cases where both the physical mapping of the data or the number of processing nodes are known at compilation time. In this paper, a novel application of the inspector-executor model overcomes these limitations and allows profitable code transformations, which result in fewer and larger messages sent through the network, when neither the data mapping nor the number of processing nodes are known at compilation time. A performance evaluation reports both scaling and absolute performance numbers on up to 32,768 cores of a Power 775 supercomputer. This evaluation indicates that the compiler transformation results in speedups between 1.15× and 21 × over a baseline and that these automated transformations achieve up to 63 percent the performance of the MPI versions. |
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