On the design and characterization of femtoampere current-mode circuits

In this paper, we show and validate a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes. The technique involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents. It also...

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Detalles Bibliográficos
Autores: Linares Barranco, Bernabé, Serrano Gotarredona, María Teresa
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2003
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/76267
Acceso en línea:https://hdl.handle.net/11441/76267
https://doi.org/10.1109/JSSC.2003.814415
Access Level:acceso abierto
Palabra clave:Analog VLSI design
Leakage currents
Mismatch
Subthreshold
Ultralow currents
Weak inversion
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spelling On the design and characterization of femtoampere current-mode circuitsLinares Barranco, BernabéSerrano Gotarredona, María TeresaAnalog VLSI designLeakage currentsMismatchSubthresholdUltralow currentsWeak inversionIn this paper, we show and validate a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes. The technique involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents. It also uses a special on-chip sawtooth oscillator to monitor and measure currents down to a few femtoamperes. This way, subpicoampere currents are characterized without driving them off chip and requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is Implemented that uses a 100-fF capacitor and a 3.5-fA bias current to achieve a cutoff frequency of 0.5 Hz. A technique for characterizing noise at these currents is also described and verified. Finally, transistor mismatch measurements are provided and discussed. Experimental measurements are shown throughout the paper, obtained from prototypes fabricated in the AMS 0.35-μm three-metal two-poly standard CMOS process.Ministerio de Ciencia y Tecnología TIC-1999-0446-C02-02, FIT-070000-2001-0859, TIC-2000-0406-P4-05, TIC-2002-10878-EEuropean Union IST-2001-34124Institute of Electrical and Electronics EngineersArquitectura y Tecnología de ComputadoresMinisterio de Ciencia y Tecnología (MCYT). EspañaEuropean Union (UE)2003info:eu-repo/semantics/articleinfo:eu-repo/semantics/acceptedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/76267https://doi.org/10.1109/JSSC.2003.814415reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésIEEE Journal of Solid-State Circuits, 38 (8), 1353-1363.TIC-1999-0446-C02-02FIT-070000-2001-0859TIC-2000-0406-P4-05TIC-2002-10878-EIST-2001-34124http://dx.doi.org/10.1109/JSSC.2003.814415info:eu-repo/semantics/openAccessoai:idus.us.es:11441/762672026-06-17T12:51:07Z
dc.title.none.fl_str_mv On the design and characterization of femtoampere current-mode circuits
title On the design and characterization of femtoampere current-mode circuits
spellingShingle On the design and characterization of femtoampere current-mode circuits
Linares Barranco, Bernabé
Analog VLSI design
Leakage currents
Mismatch
Subthreshold
Ultralow currents
Weak inversion
title_short On the design and characterization of femtoampere current-mode circuits
title_full On the design and characterization of femtoampere current-mode circuits
title_fullStr On the design and characterization of femtoampere current-mode circuits
title_full_unstemmed On the design and characterization of femtoampere current-mode circuits
title_sort On the design and characterization of femtoampere current-mode circuits
dc.creator.none.fl_str_mv Linares Barranco, Bernabé
Serrano Gotarredona, María Teresa
author Linares Barranco, Bernabé
author_facet Linares Barranco, Bernabé
Serrano Gotarredona, María Teresa
author_role author
author2 Serrano Gotarredona, María Teresa
author2_role author
dc.contributor.none.fl_str_mv Arquitectura y Tecnología de Computadores
Ministerio de Ciencia y Tecnología (MCYT). España
European Union (UE)
dc.subject.none.fl_str_mv Analog VLSI design
Leakage currents
Mismatch
Subthreshold
Ultralow currents
Weak inversion
topic Analog VLSI design
Leakage currents
Mismatch
Subthreshold
Ultralow currents
Weak inversion
description In this paper, we show and validate a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes. The technique involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents. It also uses a special on-chip sawtooth oscillator to monitor and measure currents down to a few femtoamperes. This way, subpicoampere currents are characterized without driving them off chip and requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is Implemented that uses a 100-fF capacitor and a 3.5-fA bias current to achieve a cutoff frequency of 0.5 Hz. A technique for characterizing noise at these currents is also described and verified. Finally, transistor mismatch measurements are provided and discussed. Experimental measurements are shown throughout the paper, obtained from prototypes fabricated in the AMS 0.35-μm three-metal two-poly standard CMOS process.
publishDate 2003
dc.date.none.fl_str_mv 2003
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/76267
https://doi.org/10.1109/JSSC.2003.814415
url https://hdl.handle.net/11441/76267
https://doi.org/10.1109/JSSC.2003.814415
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv IEEE Journal of Solid-State Circuits, 38 (8), 1353-1363.
TIC-1999-0446-C02-02
FIT-070000-2001-0859
TIC-2000-0406-P4-05
TIC-2002-10878-E
IST-2001-34124
http://dx.doi.org/10.1109/JSSC.2003.814415
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.300724

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