AC mains synchronization loop for precalculated-based PFC converters using the output voltage measure
Common implementations of power factor correction include sensors for the input and output voltages and the input current. Many alternatives have been considered to reduce the number of sensors, especially the current sensor. One strategy is to precalculate the duty cycles that must be applied to ev...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2018 |
| País: | España |
| Institución: | Universidad Autónoma de Madrid |
| Repositorio: | Biblos-e Archivo. Repositorio Institucional de la UAM |
| Idioma: | inglés |
| OAI Identifier: | oai:repositorio.uam.es:10486/688355 |
| Acceso en línea: | http://hdl.handle.net/10486/688355 https://dx.doi.org/10.3390/electronics8010004 |
| Access Level: | acceso abierto |
| Palabra clave: | AC-DC power conversion Digital control Field programmable gate arrays Power factor Informática |
| Sumario: | Common implementations of power factor correction include sensors for the input and output voltages and the input current. Many alternatives have been considered to reduce the number of sensors, especially the current sensor. One strategy is to precalculate the duty cycles that must be applied to every ac main, so the system only needs to synchronize them with the input voltage, and include a simple output voltage loop. The main problem with this approach is the sensibility to any synchronization error, because the input current is not measured, so its evolution is not continuously corrected. This paper shows how the synchronization error alters the current and the power factor, and it proposes several methods to detect and correct this error. All methods use the output voltage ADC, which is already used to control the output voltage, so the cost of the system is not increased. This technique can also be applied to any current sensorless PFC converter, because they are usually affected by leading or lagging currents, so the synchronization can be modified to reduce these effects. Results show that the implementation of this synchronization loop keeps a high-power factor under a wide synchronization error range, while the added logic is not significant. |
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