Modeling and analysis of link-layer protocols for multi-chip quantum computers

Quantum computers promise exponential speedups over classical computers for a specific set of problems, yet scaling quantum systems to the sizes required for practical applications remains a major challenge. Multi-chip architectures promise improved scalability and reduced per-chip complexity by int...

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Detalles Bibliográficos
Autor: Zeising, Michael
Tipo de recurso: tesis de maestría
Fecha de publicación:2026
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:dnet:upcommonspor::252377ba53d04152da381d3fa8690811
Acceso en línea:https://hdl.handle.net/2117/460883
Access Level:acceso abierto
Palabra clave:Quantum computing
Computer architecture
Computer network protocols
Computació quàntica
Arquitectures modulars
Comunicació quàntica
Protocols de capa d'enllaç
Escalabilitat
Modular architectures
Quantum communication
Link-layer protocols
Scalability
Arquitectura d'ordinadors
Protocols de xarxes d'ordinadors
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Descripción
Sumario:Quantum computers promise exponential speedups over classical computers for a specific set of problems, yet scaling quantum systems to the sizes required for practical applications remains a major challenge. Multi-chip architectures promise improved scalability and reduced per-chip complexity by interconnecting quantum processors via quantum links. The performance of these interconnects is a key factor determining overall system performance and, ultimately, the feasibility of modular quantum computing. This master's thesis investigates the modeling and analysis of link-layer protocols for multi-chip quantum computers. In this work, various protocols for communication and interaction between chips are modeled, including Teledata, Telegate, and entanglement swapping. The impact of different architectural decisions like the number of qubits per chip and the speed of the classical network on overall performance is analyzed using detailed timing models. The results show that the choice of architecture, network speed, and selected communication protocols have a significant impact on execution time. These findings provide important insights into the scalability of future quantum computing architectures.