Mecanismos de gestión de escrituras en sistemas con tecnologías de memoria no volátiles
Since the beginning of computer systems, the memory subsystem has always been one of their essential components. However, the different pace of change between microprocessor and memory has become one of the greatest challenges that current designers have to address in order to develop more powerful...
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| Tipo de documento: | tese |
| Data de publicação: | 2017 |
| País: | España |
| Recursos: | Universidad Complutense de Madrid (UCM) |
| Repositório: | Docta Complutense |
| Idioma: | inglês |
| OAI Identifier: | oai:docta.ucm.es:20.500.14352/22357 |
| Acesso em linha: | https://hdl.handle.net/20.500.14352/22357 |
| Access Level: | Acceso aberto |
| Palavra-chave: | 004.33(043.3) 004.25(043.3) PCM Phase Change Memory Endurance Failing Cells Memory Hierarchy Cache Replacement Policies gem5 STT-RAM Reuse Detector Reuse Locality Write Reduction Energy Savings Performance Performance Monitoring Counters PMCTrack Cache Monitoring Intel CMT Memoria de Cambio de Fase Durabilidad Celdas Defectuosas Jerarquía de Memoria Políticas de Reemplazo de Cache Reducción de Escrituras Detector de Reuso Localidad de Reuso Ahorro de Energía Rendimiento Contadores de Monitorización de Rendimiento Monitorización de Cache Informática (Informática) Hardware 1203.17 Informática |
| Resumo: | Since the beginning of computer systems, the memory subsystem has always been one of their essential components. However, the different pace of change between microprocessor and memory has become one of the greatest challenges that current designers have to address in order to develop more powerful computer systems. This problem, called memory gap, is further compounded by the limited scalability and the high energy consumption of conventional memory technologies (DRAM and SRAM), which has leaded to consider new non-volatile memory (NVM) technologies as potential candidates to replace them. Among NVMs, PCM and STT-RAM are currently postulated as the best alternatives. Although PCM and STT-RAM have significant advantages over DRAM and SRAM, they also suffer from some drawbacks that need to be mitigated before they can both be employed as memory technologies for the next computers generation. Notably, the slow and energy-hungry write operations on both technologies, and the limited endurance of PCM cells, which become unchangeable after performing a relatively reduced amount of writes on them, are the main constraints of PCM and STT-RAM technologies. This thesis presents two proposals aimed to efficiently manage the write operations on this kind of memories... |
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