Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders

[EN] Stochastic low-density parity-check decoders (SLDPCs) have found favor recently both for correcting transmission errors as well as for improving the hardware efficiency. The main drawback of these decoders is that they require hundreds of time periods to decode each frame, but their chip area i...

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Autores: Pérez Pascual, Mª Asunción|||0000-0002-6925-6878, Hamilton, Alex, Maunder, Robert G., Hanzo, Lajos
Formato: artículo
Fecha de publicación:2018
País:España
Recursos:Universitat Politècnica de València (UPV)
Repositorio:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
Idioma:inglés
OAI Identifier:oai:riunet.upv.es:10251/123257
Acesso em linha:https://riunet.upv.es/handle/10251/123257
Access Level:acceso abierto
Palavra-chave:EXIT chart
Low-density parity-check decoder
Stochastic arithmetic
TECNOLOGIA ELECTRONICA
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oai_identifier_str oai:riunet.upv.es:10251/123257
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network_name_str España
repository_id_str
spelling Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check DecodersPérez Pascual, Mª Asunción|||0000-0002-6925-6878Hamilton, AlexMaunder, Robert G.Hanzo, LajosEXIT chartLow-density parity-check decoderStochastic arithmeticTECNOLOGIA ELECTRONICA[EN] Stochastic low-density parity-check decoders (SLDPCs) have found favor recently both for correcting transmission errors as well as for improving the hardware efficiency. The main drawback of these decoders is that they require hundreds of time periods to decode each frame, but their chip area is smaller than that of their fixed-point counterparts, so they can achieve higher hardware efficiency and may consume less energy. In this paper, we propose a novel extrinsic information transfer chart technique for characterizing the iterative decoding convergence of all the sequences involved in the SLDPC. We have conceived a new model, which takes into consideration not only the sequences exchanged between the decoders but also the sequences generated inside the variable-node decoder (those which are stored in the edge memories). In this way, the model is able to predict the number of decoding iterations required for achieving iterative decoding convergence, as confirmed by own decoder simulations. The proposed technique offers new insights into the operation of SLDPCs, which will facilitate improved designs for the research community.Professor L. Hanzo would like to give thanks to the ERC for the financial support of this Advanced Fellow Grant.Institute of Electrical and Electronics EngineersDepartamento de Ingeniería ElectrónicaInstituto Universitario de Telecomunicación y Aplicaciones MultimediaEscuela Politécnica Superior de GandiaMinisterio de Economía y CompetitividadRepositorio Institucional de la Universitat Politècnica de València Riunet20182018-01-01journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttps://riunet.upv.es/handle/10251/123257reponame:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valénciainstname:Universitat Politècnica de València (UPV)InglésengMinisterio de Economía y Competitividad http://dx.doi.org/10.13039/501100003329 TEC2015-70858-C2-2-R TRATAMIENTO DIGITAL DE LA SEÑAL Y CORRECCION DE ERRORES EN TRANSMISION OPTICA MEDIANTE FIBRA MULTI-NUCLEO PARA REDES OPTICAS DE ACCESO Y DE TRANSPORTE CELULARopen accesshttp://purl.org/coar/access_right/c_abf2Reconocimiento (by)http://creativecommons.org/licenses/by/4.0/info:eu-repo/semantics/openAccessoai:riunet.upv.es:10251/1232572026-06-13T07:49:27Z
dc.title.none.fl_str_mv Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders
title Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders
spellingShingle Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders
Pérez Pascual, Mª Asunción|||0000-0002-6925-6878
EXIT chart
Low-density parity-check decoder
Stochastic arithmetic
TECNOLOGIA ELECTRONICA
title_short Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders
title_full Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders
title_fullStr Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders
title_full_unstemmed Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders
title_sort Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders
dc.creator.none.fl_str_mv Pérez Pascual, Mª Asunción|||0000-0002-6925-6878
Hamilton, Alex
Maunder, Robert G.
Hanzo, Lajos
author Pérez Pascual, Mª Asunción|||0000-0002-6925-6878
author_facet Pérez Pascual, Mª Asunción|||0000-0002-6925-6878
Hamilton, Alex
Maunder, Robert G.
Hanzo, Lajos
author_role author
author2 Hamilton, Alex
Maunder, Robert G.
Hanzo, Lajos
author2_role author
author
author
dc.contributor.none.fl_str_mv Departamento de Ingeniería Electrónica
Instituto Universitario de Telecomunicación y Aplicaciones Multimedia
Escuela Politécnica Superior de Gandia
Ministerio de Economía y Competitividad
Repositorio Institucional de la Universitat Politècnica de València Riunet
dc.subject.none.fl_str_mv EXIT chart
Low-density parity-check decoder
Stochastic arithmetic
TECNOLOGIA ELECTRONICA
topic EXIT chart
Low-density parity-check decoder
Stochastic arithmetic
TECNOLOGIA ELECTRONICA
description [EN] Stochastic low-density parity-check decoders (SLDPCs) have found favor recently both for correcting transmission errors as well as for improving the hardware efficiency. The main drawback of these decoders is that they require hundreds of time periods to decode each frame, but their chip area is smaller than that of their fixed-point counterparts, so they can achieve higher hardware efficiency and may consume less energy. In this paper, we propose a novel extrinsic information transfer chart technique for characterizing the iterative decoding convergence of all the sequences involved in the SLDPC. We have conceived a new model, which takes into consideration not only the sequences exchanged between the decoders but also the sequences generated inside the variable-node decoder (those which are stored in the edge memories). In this way, the model is able to predict the number of decoding iterations required for achieving iterative decoding convergence, as confirmed by own decoder simulations. The proposed technique offers new insights into the operation of SLDPCs, which will facilitate improved designs for the research community.
publishDate 2018
dc.date.none.fl_str_mv 2018
2018-01-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://riunet.upv.es/handle/10251/123257
url https://riunet.upv.es/handle/10251/123257
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.relation.none.fl_str_mv Ministerio de Economía y Competitividad http://dx.doi.org/10.13039/501100003329 TEC2015-70858-C2-2-R TRATAMIENTO DIGITAL DE LA SEÑAL Y CORRECCION DE ERRORES EN TRANSMISION OPTICA MEDIANTE FIBRA MULTI-NUCLEO PARA REDES OPTICAS DE ACCESO Y DE TRANSPORTE CELULAR
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Reconocimiento (by)
http://creativecommons.org/licenses/by/4.0/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Reconocimiento (by)
http://creativecommons.org/licenses/by/4.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
dc.source.none.fl_str_mv reponame:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname:Universitat Politècnica de València (UPV)
instname_str Universitat Politècnica de València (UPV)
reponame_str RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
collection RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869405572799922176
score 15.301603

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