FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converter

With the aim to implement a suitable controller for a three-phase dc-ac multilevel active-clamped converter to enable its use in practice, and as a first step toward a full closed-loop converter control implementation into a single field-programmable gate array (FPGA) device, this paper presents the...

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Autores: Lupón Roses, Emilio|||0000-0001-7304-271X, Busquets Monge, Sergio|||0000-0002-8613-1110, Nicolás Apruzzese, Joan|||0000-0001-7566-7721
Tipo de recurso: artículo
Fecha de publicación:2014
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/23223
Acceso en línea:https://hdl.handle.net/2117/23223
https://dx.doi.org/10.1109/TII.2014.2309483
Access Level:acceso abierto
Palabra clave:Electronic circuits
Field-programmable gate array (FPGA)
multilevel active-clamped (MAC) converter
pulsewidth modulation (PWM)
Circuits electrònics
Àrees temàtiques de la UPC::Enginyeria electrònica::Optoelectrònica
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spelling FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converterLupón Roses, Emilio|||0000-0001-7304-271XBusquets Monge, Sergio|||0000-0002-8613-1110Nicolás Apruzzese, Joan|||0000-0001-7566-7721Electronic circuitsField-programmable gate array (FPGA)multilevel active-clamped (MAC) converterpulsewidth modulation (PWM)Circuits electrònicsÀrees temàtiques de la UPC::Enginyeria electrònica::OptoelectrònicaWith the aim to implement a suitable controller for a three-phase dc-ac multilevel active-clamped converter to enable its use in practice, and as a first step toward a full closed-loop converter control implementation into a single field-programmable gate array (FPGA) device, this paper presents the structure and features of an FPGA implementation of an appropriate pulsewidth modulation (PWM) strategy. The selected PWM strategy guarantees dc-link capacitor voltage balance in every switching cycle, and covers both the undermodulation and overmodulation regions. A flexible implementation is conceived, allowing the variation of important operating parameters, such as the modulation index and switching frequency, through a simple user interface. The key aspects to achieve an efficient and robust FPGA implementation are discussed. Experimental results in a four-level converter prototype controlled with an Altera Cyclone III device under different operating conditions match fairly well with the expected results obtained through simulation, thus verifying the accurate performance of the FPGA-based modulator20142014-05-0120142014-06-14journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/2117/23223https://dx.doi.org/10.1109/TII.2014.2309483reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/232232026-05-27T15:37:01Z
dc.title.none.fl_str_mv FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converter
title FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converter
spellingShingle FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converter
Lupón Roses, Emilio|||0000-0001-7304-271X
Electronic circuits
Field-programmable gate array (FPGA)
multilevel active-clamped (MAC) converter
pulsewidth modulation (PWM)
Circuits electrònics
Àrees temàtiques de la UPC::Enginyeria electrònica::Optoelectrònica
title_short FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converter
title_full FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converter
title_fullStr FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converter
title_full_unstemmed FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converter
title_sort FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converter
dc.creator.none.fl_str_mv Lupón Roses, Emilio|||0000-0001-7304-271X
Busquets Monge, Sergio|||0000-0002-8613-1110
Nicolás Apruzzese, Joan|||0000-0001-7566-7721
author Lupón Roses, Emilio|||0000-0001-7304-271X
author_facet Lupón Roses, Emilio|||0000-0001-7304-271X
Busquets Monge, Sergio|||0000-0002-8613-1110
Nicolás Apruzzese, Joan|||0000-0001-7566-7721
author_role author
author2 Busquets Monge, Sergio|||0000-0002-8613-1110
Nicolás Apruzzese, Joan|||0000-0001-7566-7721
author2_role author
author
dc.subject.none.fl_str_mv Electronic circuits
Field-programmable gate array (FPGA)
multilevel active-clamped (MAC) converter
pulsewidth modulation (PWM)
Circuits electrònics
Àrees temàtiques de la UPC::Enginyeria electrònica::Optoelectrònica
topic Electronic circuits
Field-programmable gate array (FPGA)
multilevel active-clamped (MAC) converter
pulsewidth modulation (PWM)
Circuits electrònics
Àrees temàtiques de la UPC::Enginyeria electrònica::Optoelectrònica
description With the aim to implement a suitable controller for a three-phase dc-ac multilevel active-clamped converter to enable its use in practice, and as a first step toward a full closed-loop converter control implementation into a single field-programmable gate array (FPGA) device, this paper presents the structure and features of an FPGA implementation of an appropriate pulsewidth modulation (PWM) strategy. The selected PWM strategy guarantees dc-link capacitor voltage balance in every switching cycle, and covers both the undermodulation and overmodulation regions. A flexible implementation is conceived, allowing the variation of important operating parameters, such as the modulation index and switching frequency, through a simple user interface. The key aspects to achieve an efficient and robust FPGA implementation are discussed. Experimental results in a four-level converter prototype controlled with an Altera Cyclone III device under different operating conditions match fairly well with the expected results obtained through simulation, thus verifying the accurate performance of the FPGA-based modulator
publishDate 2014
dc.date.none.fl_str_mv 2014
2014-05-01
2014
2014-06-14
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/23223
https://dx.doi.org/10.1109/TII.2014.2309483
url https://hdl.handle.net/2117/23223
https://dx.doi.org/10.1109/TII.2014.2309483
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,301603

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