A Formalization of Kannan’s Circuit Lower Bound in Bounded Arithmetic

Treballs Finals del Màster de Lògica Pura i Aplicada, Facultat de Filosofia, Universitat de Barcelona. Curs: 2024-2024. Tutor: Albert Atserias

Detalles Bibliográficos
Autor: Cantero de Arriba, Carlos
Tipo de recurso: tesis de maestría
Fecha de publicación:2024
País:España
Institución:Universidad de Barcelona
Repositorio:Dipòsit Digital de la UB
OAI Identifier:oai:diposit.ub.edu:2445/215181
Acceso en línea:https://hdl.handle.net/2445/215181
Access Level:acceso abierto
Palabra clave:Lògica matemática
Complexitat computacional
Circuits integrats
Treballs de fi de màster
Mathematical logic
Computational complexity
Integrated circuits
Master's thesis
id ES_2e79cc8f57d7ec02ebd4f4358f56b7ab
oai_identifier_str oai:diposit.ub.edu:2445/215181
network_acronym_str ES
network_name_str España
repository_id_str
spelling A Formalization of Kannan’s Circuit Lower Bound in Bounded ArithmeticCantero de Arriba, CarlosLògica matemáticaComplexitat computacionalCircuits integratsTreballs de fi de màsterMathematical logicComputational complexityIntegrated circuitsMaster's thesisTreballs Finals del Màster de Lògica Pura i Aplicada, Facultat de Filosofia, Universitat de Barcelona. Curs: 2024-2024. Tutor: Albert AtseriasThe aim of this work is to formalize the circuit-size lower bound showed by Kannan in 1982 in a weak theory for feasible computations. In particular, we will work with theories of bounded arithmetic, which are subtheories of Peano Arithmetic that weaken its induction axiom scheme by restricting it to formulas in which the quantifiers are bounded. Kannan’s circuit lower bound states that for every fixed polynomial size of circuits, there is a language in the second level of the polynomial hierarchy that cannot be decided by circuits of that size. We note that the essential ingredient in this proof is a key use of the weak pigeonhole principle, which is available in bounded arithmetic. Instrumental in the proof of Kannan’s Theorem is the celebrated Karp-Lipton’s Theorem, stating that if the satisfiability problem for propositional formulas can be decided by polynomial-size circuits then the polynomial hierarchy collapses to its second level, which we also formalize in the same theoryAtserias, Albert2024info:eu-repo/semantics/masterThesisapplication/pdfhttps://hdl.handle.net/2445/215181Màster Oficial - Pure and Applied Logic / Lògica Pura i aplicadareponame:Dipòsit Digital de la UBinstname:Universidad de BarcelonaIngléscc by-nc-nd (c) Cantero, 2024http://creativecommons.org/licenses/by-nc-nd/3.0/es/info:eu-repo/semantics/openAccessoai:diposit.ub.edu:2445/2151812026-05-27T06:46:51Z
dc.title.none.fl_str_mv A Formalization of Kannan’s Circuit Lower Bound in Bounded Arithmetic
title A Formalization of Kannan’s Circuit Lower Bound in Bounded Arithmetic
spellingShingle A Formalization of Kannan’s Circuit Lower Bound in Bounded Arithmetic
Cantero de Arriba, Carlos
Lògica matemática
Complexitat computacional
Circuits integrats
Treballs de fi de màster
Mathematical logic
Computational complexity
Integrated circuits
Master's thesis
title_short A Formalization of Kannan’s Circuit Lower Bound in Bounded Arithmetic
title_full A Formalization of Kannan’s Circuit Lower Bound in Bounded Arithmetic
title_fullStr A Formalization of Kannan’s Circuit Lower Bound in Bounded Arithmetic
title_full_unstemmed A Formalization of Kannan’s Circuit Lower Bound in Bounded Arithmetic
title_sort A Formalization of Kannan’s Circuit Lower Bound in Bounded Arithmetic
dc.creator.none.fl_str_mv Cantero de Arriba, Carlos
author Cantero de Arriba, Carlos
author_facet Cantero de Arriba, Carlos
author_role author
dc.contributor.none.fl_str_mv Atserias, Albert
dc.subject.none.fl_str_mv Lògica matemática
Complexitat computacional
Circuits integrats
Treballs de fi de màster
Mathematical logic
Computational complexity
Integrated circuits
Master's thesis
topic Lògica matemática
Complexitat computacional
Circuits integrats
Treballs de fi de màster
Mathematical logic
Computational complexity
Integrated circuits
Master's thesis
description Treballs Finals del Màster de Lògica Pura i Aplicada, Facultat de Filosofia, Universitat de Barcelona. Curs: 2024-2024. Tutor: Albert Atserias
publishDate 2024
dc.date.none.fl_str_mv 2024
dc.type.none.fl_str_mv info:eu-repo/semantics/masterThesis
format masterThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/2445/215181
url https://hdl.handle.net/2445/215181
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.rights.none.fl_str_mv cc by-nc-nd (c) Cantero, 2024
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
info:eu-repo/semantics/openAccess
rights_invalid_str_mv cc by-nc-nd (c) Cantero, 2024
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv Màster Oficial - Pure and Applied Logic / Lògica Pura i aplicada
reponame:Dipòsit Digital de la UB
instname:Universidad de Barcelona
instname_str Universidad de Barcelona
reponame_str Dipòsit Digital de la UB
collection Dipòsit Digital de la UB
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869405407369232384
score 15,811543

Similares en LA Referencia