Low-Cost Full Correlated-Power-Noise Generator to Counteract Side-Channel Attacks
Considerable attention has been given to addressing side-channel attacks to improve the security of cryptographic hardware implementations. These attacks encourage the exploration of various countermeasures across different levels of abstraction, through masking and hiding techniques, mainly. In thi...
| Authors: | , , , |
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| Format: | article |
| Status: | Published version |
| Publication Date: | 2025 |
| Country: | España |
| Institution: | Universidad de Sevilla (US) |
| Repository: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/171312 |
| Online Access: | https://hdl.handle.net/11441/171312 https://doi.org/10.3390/app15063064 |
| Access Level: | Open access |
| Keyword: | CPA attacks Hiding countermeasures Correlated power noise generator FPGA AES Hardware security |
| Summary: | Considerable attention has been given to addressing side-channel attacks to improve the security of cryptographic hardware implementations. These attacks encourage the exploration of various countermeasures across different levels of abstraction, through masking and hiding techniques, mainly. In this paper, we introduce a novel hiding countermeasure designed to mitigate Correlation Power Analysis (CPA) attacks without significant overhead. The new countermeasure interferes with the processed data, minimizing the power correlation with the secret key. The proposed method involves using a Correlated-Power-Noise Generator (CPNG). This study is supported by experimental results using CPA attacks on a SAKURA-G board with a SPARTAN-6 Xilinx FPGA. An Advanced Encryption Standard (AES) cipher with 128/256-bit key size is employed for this purpose. The proposed secure design of AES has an area overhead of 29.04% compared to unprotected AES. After conducting a CPA attack, the acquisition of information about the private key has been reduced drastically by 44.5%. |
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