A 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculation
A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 ± pp-d (pm 1.33~V{REF}). The circuit also includes a comparator of...
| Autores: | , , , , , |
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| Formato: | artículo |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2018 |
| País: | España |
| Recursos: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repositorio: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/195630 |
| Acesso em linha: | http://hdl.handle.net/10261/195630 |
| Access Level: | acceso abierto |
| Palavra-chave: | Feedback control system SAR Comparator offset Capacitor segmentation Analog-to-digital converters |
| Resumo: | A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 ± pp-d (pm 1.33~V{REF}). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-μ m CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB. |
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