Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpga

Hardware-in-the-loop (HIL) simulations of power converters must achieve a truthful representation in real time with simulation steps on the order of microseconds or tens of nanoseconds. The numerical solution for the differential equations that model the state of the converter can be calculated usin...

Descripción completa

Detalles Bibliográficos
Autores: Saralegui, Roberto, Sánchez González, Alberto, Castro Martín, Ángel de
Tipo de recurso: artículo
Fecha de publicación:2021
País:España
Institución:Universidad Autónoma de Madrid
Repositorio:Biblos-e Archivo. Repositorio Institucional de la UAM
Idioma:inglés
OAI Identifier:oai:repositorio.uam.es:10486/701133
Acceso en línea:http://hdl.handle.net/10486/701133
https://dx.doi.org/10.3390/app11146490
Access Level:acceso abierto
Palabra clave:Field programmable gate array
Fixed-point
Floating-point
Hardware-in-the-loop
Real-time emulation
Telecomunicaciones
id ES_22b9ddfbaf6fee290103e875b2b8b992
oai_identifier_str oai:repositorio.uam.es:10486/701133
network_acronym_str ES
network_name_str España
repository_id_str
spelling Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpgaSaralegui, RobertoSánchez González, AlbertoCastro Martín, Ángel deField programmable gate arrayFixed-pointFloating-pointHardware-in-the-loopReal-time emulationTelecomunicacionesHardware-in-the-loop (HIL) simulations of power converters must achieve a truthful representation in real time with simulation steps on the order of microseconds or tens of nanoseconds. The numerical solution for the differential equations that model the state of the converter can be calculated using the fourth-order Runge–Kutta method, which is notably more accurate than Euler methods. However, when the mathematical error due to the solver is drastically reduced, other sources of error arise. In the case of converters that use deadtimes to control the switches, such as any power converter including half-bridge modules, the inductor current reaching zero during deadtimes generates a model error large enough to offset the advantages of the Runge–Kutta method. A specific model is needed for such events. In this paper, an approximation is proposed, where the time step is divided into two semi-steps. This serves to recover the accuracy of the calculations at the expense of needing a division operation. A fixed-point implementation in VHDL is proposed, reusing a block along several calculation cycles to compute the needed parameters for the Runge–Kutta method. The implementation in a low-cost field-programmable gate arrays (FPGA) (Xilinx Artix-7) achieves an integration time of 1 µs. The calculation errors are six orders of magnitude smaller for both capacitor voltage and inductor current for the worst case, the one where the current reaches zero during the deadtimes in 78% of the simulated cycles. The accuracy achieved with the proposed fixed point implementation is very close to that of 64-bit floating point and can operate in real time with a resolution of 1 µs. Therefore, the results show that this approach is suitable for modeling converters based on half-bridge modules by using FPGAs. This solution is intended for easy integration into any HIL system, including commercial HIL systems, showing that its application even with relatively high integration steps (1 µs) surpasses the results of techniques with even faster integration steps that do not take these events into accountMDPIDepartamento de Tecnología Electrónica y de las ComunicacionesEscuela Politécnica SuperiorHardware and Control Technology Laboratory20212021-07-14research articlehttp://purl.org/coar/resource_type/c_2df8fbb1VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10486/701133https://dx.doi.org/10.3390/app11146490reponame:Biblos-e Archivo. Repositorio Institucional de la UAMinstname:Universidad Autónoma de MadridInglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:repositorio.uam.es:10486/7011332026-06-23T12:46:27Z
dc.title.none.fl_str_mv Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpga
title Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpga
spellingShingle Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpga
Saralegui, Roberto
Field programmable gate array
Fixed-point
Floating-point
Hardware-in-the-loop
Real-time emulation
Telecomunicaciones
title_short Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpga
title_full Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpga
title_fullStr Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpga
title_full_unstemmed Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpga
title_sort Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpga
dc.creator.none.fl_str_mv Saralegui, Roberto
Sánchez González, Alberto
Castro Martín, Ángel de
author Saralegui, Roberto
author_facet Saralegui, Roberto
Sánchez González, Alberto
Castro Martín, Ángel de
author_role author
author2 Sánchez González, Alberto
Castro Martín, Ángel de
author2_role author
author
dc.contributor.none.fl_str_mv Departamento de Tecnología Electrónica y de las Comunicaciones
Escuela Politécnica Superior
Hardware and Control Technology Laboratory
dc.subject.none.fl_str_mv Field programmable gate array
Fixed-point
Floating-point
Hardware-in-the-loop
Real-time emulation
Telecomunicaciones
topic Field programmable gate array
Fixed-point
Floating-point
Hardware-in-the-loop
Real-time emulation
Telecomunicaciones
description Hardware-in-the-loop (HIL) simulations of power converters must achieve a truthful representation in real time with simulation steps on the order of microseconds or tens of nanoseconds. The numerical solution for the differential equations that model the state of the converter can be calculated using the fourth-order Runge–Kutta method, which is notably more accurate than Euler methods. However, when the mathematical error due to the solver is drastically reduced, other sources of error arise. In the case of converters that use deadtimes to control the switches, such as any power converter including half-bridge modules, the inductor current reaching zero during deadtimes generates a model error large enough to offset the advantages of the Runge–Kutta method. A specific model is needed for such events. In this paper, an approximation is proposed, where the time step is divided into two semi-steps. This serves to recover the accuracy of the calculations at the expense of needing a division operation. A fixed-point implementation in VHDL is proposed, reusing a block along several calculation cycles to compute the needed parameters for the Runge–Kutta method. The implementation in a low-cost field-programmable gate arrays (FPGA) (Xilinx Artix-7) achieves an integration time of 1 µs. The calculation errors are six orders of magnitude smaller for both capacitor voltage and inductor current for the worst case, the one where the current reaches zero during the deadtimes in 78% of the simulated cycles. The accuracy achieved with the proposed fixed point implementation is very close to that of 64-bit floating point and can operate in real time with a resolution of 1 µs. Therefore, the results show that this approach is suitable for modeling converters based on half-bridge modules by using FPGAs. This solution is intended for easy integration into any HIL system, including commercial HIL systems, showing that its application even with relatively high integration steps (1 µs) surpasses the results of techniques with even faster integration steps that do not take these events into account
publishDate 2021
dc.date.none.fl_str_mv 2021
2021-07-14
dc.type.none.fl_str_mv research article
http://purl.org/coar/resource_type/c_2df8fbb1
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv http://hdl.handle.net/10486/701133
https://dx.doi.org/10.3390/app11146490
url http://hdl.handle.net/10486/701133
https://dx.doi.org/10.3390/app11146490
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv MDPI
publisher.none.fl_str_mv MDPI
dc.source.none.fl_str_mv reponame:Biblos-e Archivo. Repositorio Institucional de la UAM
instname:Universidad Autónoma de Madrid
instname_str Universidad Autónoma de Madrid
reponame_str Biblos-e Archivo. Repositorio Institucional de la UAM
collection Biblos-e Archivo. Repositorio Institucional de la UAM
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869404598697984000
score 15,300724

Similares en LA Referencia