FPGA and ASIC accelerators for genome data analysis
(English) The continuous progress of Moore’s Law in improving single-threaded performance (execution time) through clock frequency and process node improvements has slowed down due to physical limitations in silicon device physics. This has resulted in a shift towards using multicore processors to a...
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| Tipo de recurso: | tesis doctoral |
| Estado: | Versión publicada |
| Fecha de publicación: | 2024 |
| País: | España |
| Institución: | CBUC, CESCA |
| Repositorio: | TDR. Tesis Doctorales en Red |
| OAI Identifier: | oai:www.tdx.cat:10803/692984 |
| Acceso en línea: | http://hdl.handle.net/10803/692984 https://dx.doi.org/10.5821/dissertation-2117-421134 |
| Access Level: | acceso abierto |
| Palabra clave: | Àrees temàtiques de la UPC::Informàtica 004 575 |
| Sumario: | (English) The continuous progress of Moore’s Law in improving single-threaded performance (execution time) through clock frequency and process node improvements has slowed down due to physical limitations in silicon device physics. This has resulted in a shift towards using multicore processors to achieve performance gains. However, the use of multiprocessing is limited by Amdahl’s Law, in which the sequential parts of the applications restrict the speedups in parallel systems. Consequently, the technology industry is now emphasizing specialization and developing domain-specific accelerators to enhance performance compared to general-purpose computers. Genomics is a field that deals with the study of genes and their functions. Thanks to current and ongoing advancements, each stage of development in sequencing technologies is able to produce enormous amounts of data at an increasingly faster and cheaper way compared to its previous stage. However, the assembly and analysis of this data take extensive time on general- purpose processors, and the processor performance is growing at a much slower pace than the DNA sequencing speed. Hence, domain-specific accelerators are becoming increasingly essential in the genomics field, especially for DNA assembly. Specialized hardware computing devices designed for this specific domain can achieve significant performance improvements compared to general-purpose computers. Thus, with domain-specific accelerators, the speed of DNA assembly can keep up with the pace of DNA sequencing, allowing for quicker analysis and discoveries in the genomics field. The main goal of this thesis is to accelerate two critical applications of DNA assembly, k-mer counting and pairwise read alignment, using FPGAs and ASICs. The first contribution of this thesis targets accelerating the k-mer counting application using FPGAs and its adaptation in a genomics application called SMUFIN, a Somatic MUtation FINder. The second and third contributions focus on exploiting FPGAs for accelerating the Wavefront Alignment (WFA), a novel pairwise read alignment algorithm for aligning DNA sequences generated by different sequencing technologies. The accelerator in the second contribution is customized for short DNA sequences of up to 300 bases, which are generated by next generation sequencing technologies, while the accelerator in the third contribution is customized for long DNA sequences of up to 50K bases, which are generated by third generation sequencing technologies. The fourth contribution proposes an ASIC accelerator of the WFA algorithm and its integration in a RISC-V SoC. In all contributions, we analyze different parts of the application and port the most time-consuming parts to the accelerator. We also modify and re-design the remaining CPU parts to better adapt them to the accelerator code and finally propose efficient co-designed accelerated designs. In our first contribution, the integration of our k-mer counting accelerator improves the SMUFIN k-mer counting performance by 2.14× while consuming 2.93× less energy and 1.57× less memory compared to the baseline multi-threaded software implementation. The performance of the WFA accelerators in the second and third contributions is evaluated using one and two FPGAs. Compared to the baseline multi-threaded software implementation of the WFA running on a IBM POWER9 high-performance processor, our WFA accelerator for short reads reaches performance improvements of up to 8.8× and 13.5× with one and two FPGAs, respectively. The WFA accelerator for long reads reaches performance improvements of up to 5.6× and 9.9× with one and two FPGAs, respectively. In our fourth contribution, our ASIC WFA accelerator integrated in the RISC-V SoC reaches performance improvements of up to 1076× compared to the single-threaded software implementation of the WFA on Sargantana, the RISC-V CPU of the chip. |
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