AER image filtering architecture for vision-processing systems
A VLSI architecture is proposed for the realization of real-time two-dimensional (2-D) image filtering in an address-event-representation (AER) vision system. The architecture is capable of implementing any convolutional kernel F(x,y) as long as it is decomposable into x-axis and y-axis components,...
| Autores: | , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 1999 |
| País: | España |
| Institución: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/76405 |
| Acceso en línea: | https://hdl.handle.net/11441/76405 https://doi.org/10.1109/81.788808 |
| Access Level: | acceso abierto |
| Palabra clave: | Analog integrated circuits Communication systems Convolution circuits Gabor filters Image analysis Image segmentation Neural networks Nonlinear circuits Subthreshold circuits |
| Sumario: | A VLSI architecture is proposed for the realization of real-time two-dimensional (2-D) image filtering in an address-event-representation (AER) vision system. The architecture is capable of implementing any convolutional kernel F(x,y) as long as it is decomposable into x-axis and y-axis components, i.e., F(x, y) = H(x)V(y), for some rotated coordinate system {x, y} and if this product can be approximated safely by a signed minimum operation. The proposed architecture is intended to be used in a complete vision system, known as the boundary contour system and feature contour system (BCS-FCS) vision model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and some electrical simulations. |
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