Analysis of error mechanisms in switched-current Sigma-Delta modulators

This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modelin...

Full description

Bibliographic Details
Authors: Rosa Utrera, José Manuel de la, Pérez Verdú, Belén, Medeiro Hidalgo, Fernando, Río Fernández, Rocío del, Rodríguez Vázquez, Ángel Benito
Format: article
Status:Versión enviada para evaluación y publicación
Publication Date:2004
Country:España
Institution:Universidad de Sevilla (US)
Repository:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/77537
Online Access:https://hdl.handle.net/11441/77537
https://doi.org/10.1023/B:ALOG.0000011167.24521.82
Access Level:Open access
Keyword:Analog-to-digital converters
Sigma-Delta modulators
Switched-current circuits
id ES_11b79beabf6591ee2e95fd50822f69fa
oai_identifier_str oai:idus.us.es:11441/77537
network_acronym_str ES
network_name_str España
repository_id_str
spelling Analysis of error mechanisms in switched-current Sigma-Delta modulatorsRosa Utrera, José Manuel de laPérez Verdú, BelénMedeiro Hidalgo, FernandoRío Fernández, Rocío delRodríguez Vázquez, Ángel BenitoAnalog-to-digital convertersSigma-Delta modulatorsSwitched-current circuitsThis paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass ΣΔM (2nd-LPΣΔM) and a 4th-order BandPass ΣΔM (4th-BPΣΔM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notch frequency position in the case of 4th-BPΣΔMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI ΣΔMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 μm CMOS SI 4th-BPΣΔM silicon prototype validate our approach.European Union IST 2001-34283Comisión Interministerial de Ciencia y Tecnología TIC2001-0929SpringerElectrónica y ElectromagnetismoEuropean Union (UE)Comisión Interministerial de Ciencia y Tecnología (CICYT). España2004info:eu-repo/semantics/articleinfo:eu-repo/semantics/submittedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/77537https://doi.org/10.1023/B:ALOG.0000011167.24521.82reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésAnalog Integrated Circuits and Signal Processing, 38 (2-3), 175-201.IST 2001-34283TIC2001-0929http://dx.doi.org/10.1023/B:ALOG.0000011167.24521.82info:eu-repo/semantics/openAccessoai:idus.us.es:11441/775372026-06-17T12:51:07Z
dc.title.none.fl_str_mv Analysis of error mechanisms in switched-current Sigma-Delta modulators
title Analysis of error mechanisms in switched-current Sigma-Delta modulators
spellingShingle Analysis of error mechanisms in switched-current Sigma-Delta modulators
Rosa Utrera, José Manuel de la
Analog-to-digital converters
Sigma-Delta modulators
Switched-current circuits
title_short Analysis of error mechanisms in switched-current Sigma-Delta modulators
title_full Analysis of error mechanisms in switched-current Sigma-Delta modulators
title_fullStr Analysis of error mechanisms in switched-current Sigma-Delta modulators
title_full_unstemmed Analysis of error mechanisms in switched-current Sigma-Delta modulators
title_sort Analysis of error mechanisms in switched-current Sigma-Delta modulators
dc.creator.none.fl_str_mv Rosa Utrera, José Manuel de la
Pérez Verdú, Belén
Medeiro Hidalgo, Fernando
Río Fernández, Rocío del
Rodríguez Vázquez, Ángel Benito
author Rosa Utrera, José Manuel de la
author_facet Rosa Utrera, José Manuel de la
Pérez Verdú, Belén
Medeiro Hidalgo, Fernando
Río Fernández, Rocío del
Rodríguez Vázquez, Ángel Benito
author_role author
author2 Pérez Verdú, Belén
Medeiro Hidalgo, Fernando
Río Fernández, Rocío del
Rodríguez Vázquez, Ángel Benito
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Electrónica y Electromagnetismo
European Union (UE)
Comisión Interministerial de Ciencia y Tecnología (CICYT). España
dc.subject.none.fl_str_mv Analog-to-digital converters
Sigma-Delta modulators
Switched-current circuits
topic Analog-to-digital converters
Sigma-Delta modulators
Switched-current circuits
description This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass ΣΔM (2nd-LPΣΔM) and a 4th-order BandPass ΣΔM (4th-BPΣΔM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notch frequency position in the case of 4th-BPΣΔMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI ΣΔMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 μm CMOS SI 4th-BPΣΔM silicon prototype validate our approach.
publishDate 2004
dc.date.none.fl_str_mv 2004
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/submittedVersion
format article
status_str submittedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/77537
https://doi.org/10.1023/B:ALOG.0000011167.24521.82
url https://hdl.handle.net/11441/77537
https://doi.org/10.1023/B:ALOG.0000011167.24521.82
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv Analog Integrated Circuits and Signal Processing, 38 (2-3), 175-201.
IST 2001-34283
TIC2001-0929
http://dx.doi.org/10.1023/B:ALOG.0000011167.24521.82
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Springer
publisher.none.fl_str_mv Springer
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869403579885813760
score 15.300724

Similar Items