Characterization of a Spiking Convolutional Processor for FPGA

In event-based neuromorphic processing, computer vision finds an efficient alternative capable of optimizing computational and energy resources, inspired by the dynamics of biological neural systems. In the development of real-time processing systems, it is crucial to visually represent the informat...

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Detalles Bibliográficos
Autores: Curra Sosa, Dagnier Antonio, Gómez Rodríguez, Francisco de Asís, Linares Barranco, Alejandro
Tipo de recurso: artículo
Estado:Versión publicada
Fecha de publicación:2026
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:dnet:idus________::b527b487b1ed58b9f3f39317ebcf36ea
Acceso en línea:https://hdl.handle.net/11441/185438
https://doi.org/10.3390/s26061801
Access Level:acceso abierto
Palabra clave:FPGA
DVS
Address-Event-Representation (AER)
Spiking Convolution Neural Network (SCNN)
LIF neuron model
Descripción
Sumario:In event-based neuromorphic processing, computer vision finds an efficient alternative capable of optimizing computational and energy resources, inspired by the dynamics of biological neural systems. In the development of real-time processing systems, it is crucial to visually represent the information captured by sensors and to explore its content with precision. Thus, machine learning models are implemented with the capability of being deployed on hardware devices with limited capabilities, depending on the intended purpose, ensuring savings in computational resources. The aim of this work was to evaluate the limits of the implemented neuron model, leaky-integrate and fire (LIF), for fitting convolutional layers of a neural network. To this end, the characteristics of the LIF neuron model used are summarized, as well as the details of its implementation in a hardware design, using configurable parameters. The experimental phase considered two convolution approaches to compare performance, Matlab R2022a software and a spiking convolutional processor for an FPGA, using sample recordings from the MNIST-DVS dataset and Sobel kernels for edge detection. The results reflect that the number of spikes generated by both approaches is very similar and their distribution by frame addresses is directly proportional.