Mitosis: A speculative multithreaded processor based on pre-computation slices
This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads. Speculative multithreading increases single-threaded application performance by exploiting thread-level parallelism spe...
| Autores: | , , , , , , , |
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| Formato: | artículo |
| Fecha de publicación: | 2008 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/100454 |
| Acesso em linha: | https://hdl.handle.net/2117/100454 https://dx.doi.org/10.1109/TPDS.2007.70797 |
| Access Level: | acceso abierto |
| Palavra-chave: | Compilers (Computer programs) Cache memory Speculative thread-level parallelism Precomputation slices Thread partitioning Multicore architecture Compiladors (Programes d'ordinador) Memòria cau Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Resumo: | This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads. Speculative multithreading increases single-threaded application performance by exploiting thread-level parallelism speculatively, that is, executing code in parallel, even when the compiler or runtime system cannot guarantee that the parallelism exists. The proposed approach is based on predicting/computing thread input values via software through a piece of code that is added at the beginning of each thread (the precomputation slice). A precomputation slice is expected to compute the correct thread input values most of the time but not necessarily always. This allows aggressive optimization techniques to be applied to the slice to make it very short. This paper focuses on the microarchitecture that supports this execution model. The primary novelty of the microarchitecture is the hardware support for the execution and validation of precomputation slices. Additionally, this paper presents new architectures for the register file and the cache memory in order to support multiple versions of each variable and allow for efficient rollback in case of misspeculation. We show that the proposed microarchitecture, together with the compiler support, achieves an average speedup of 2.2 for applications that conventional nonspeculative approaches are not able to parallelize at all. |
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